A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne.
Abstract
“Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conducted using Automatic Test Equipment (ATE) along with test infrastructures such as the Prober Interface Board (PIB), signal tower, and probe card. In this paper, we present the mechanical and electrical details of a wafer-level test infrastructure designed for higher parallel testing of system-on-chips (SoCs). In previous test infrastructures, a high site count was constrained by the available probe pins on the signal tower for wafer testing. However, the proposed signal tower addresses this bottleneck by utilizing a combination of 620 pin and 731 pin modules. This allows more probe pins to transmit signals from the ATE instrument, enabling multi-site testing. The number of available probe pins increased by 68.96% compared to the state-of-the-art infrastructure, without compromising the application area. The experimental results demonstrate that our proposed test infrastructure is suitable for mass production at the wafer-level, considering factors such as deflection, total compression forces, and electrical specifications.”
Find the technical paper here. February 2025.
S. -H. Lee, J. H. Park and Y. -W. Lee, “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip,” in IEEE Access, doi: 10.1109/ACCESS.2025.3544246.
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