Week In Review: Design, Low Power

IP, FPGA, Tools
Arm released new details on its new Neoverse N2 and Neoverse V1 platforms. A range of companies announced they will be using the platforms, including Marvell and SiPearl.

Aimed at server and HPC workloads, Neoverse V1 uses wider and deeper pipelines compared to the N1 and supports a 2x256bit wide vector unit executing the Scalable Vector Extension (SVE) instructions with support for the new bfloat16 data type for AI/ML-assisted workloads.

The Neoverse N2 is based on the new Armv9 architecture and targets a range of workloads from high-throughput computing to power and space constrained edge and 5G use-cases. It uses SVE2 for a simpler programming model, scalable SIMD vector performance, and advanced auto-vectorization capabilities. Compared to the N1, it relies less on the width and depth of the pipeline to achieve its performance.

Arm also introduced Neoverse CMN-700, a coherent mesh network to link CPUs, coherent accelerators, DDR5/HBM2e/HBM3 memory controllers, IO controllers, CCIX 2.0 bridges to external chiplets or sockets and CXL 2.0 bridges to external memory or accelerators. It can support 128+ CPUs with 40 dual-channel memory controllers, 128+ PCIe5/CCIX/CXL lanes and up to 40 general-purpose IO nodes for peripherals connected over Arm’s non-coherent network interconnect NI-700.

Xilinx is now shipping its Versal AI Core and Versal Prime adaptive compute acceleration platform devices in full production volumes. Versal AI Core is optimized for compute-intensive applications primarily for the data center, 5G wireless, and A&D markets, including machine learning and advanced signal processing, while Versal Prime series is designed for broad applicability across multiple markets, including data center workloads such as storage acceleration, firewalls and other wired communications applications.

Andes Technology uncorked its updated AndeSight IDE v5.0 for RISC-V. Aiming to accelerate AI and IoT development, it added software solutions for RISC-V DSP/SIMD and Vector extensions, a neural network library, AndesClarity processor pipeline analyzer, debugging automation and scripting, multicore debugging, and support for Linux LTS v5.4, FreeRTOS, and Zephyr.

Defacto Technologies announced SoC Compiler v9, a set of tools for front-end SoC design and IP integration. It provides IP and connectivity insertion, design editing, and views generation with real-time monitoring of the integration progress and can take in design information including RTL, IP-XACT, timing constraints, power, physical, and test. OpenFive and SiPearl noted using the product.

Standards
The Si2 Compact Model Coalition is working to fund and standardize a SPICE model for silicon carbide-based metal-on-silicon field-effect transistors. SiC MOSFETs tend to have high efficiency and fast operation with low switching losses and are seeing adoption in applications such as photovoltaic inverters and converters, industrial motor drives, EV powertrain and charging, and power supply and distribution. “I’d encourage companies with a stake in SiC devices to join this effort and help guide selection of the model which best represents their intended use,” said Peter Lee, CMC chair. “They can benefit from both cost reduction that comes from shared model support and a standardized and qualified model that has ongoing bug fixes and requested feature enhancements from many like-minded companies.”

Deals
Cadence and Arm expanded a collaboration to optimize Cadence’s digital and verification full flows for the Arm Neoverse V1 and Neoverse N2 platforms. Cadence also delivered comprehensive 5nm and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs).

Synopsys and Arm extended a strategic agreement to provide optimized EDA platforms, IP, and reference flows for Arm-based SoCs to mutual customers. It also gives Arm early access to the Synopsys DesignWare Interface IP portfolio for performance, interoperability, and compliance validation of the IP with Arm Neoverse processors. Additionally, Arm core-specific QuickStart Implementation Kits (QiKs) that include implementation scripts and reference guides are available.

Rambus and Lattice Semiconductor are teaming up to make Rambus secure hardware IP available on Lattice FPGAs for communications, computing, industrial, automotive, and consumer applications.

Arm utilized Synopsys’ Fusion Compiler RTL-to-GDSII implementation solution to optimize PPA on next-generation Arm Neoverse V1 and N2 infrastructure cores. The Synopsys and Arm reference methodology is available through QuickStart Implementation Kits.

Global Unichip Corporation (GUC) deployed the Cadence Clarity 3D Solver in its simulation workflow to design a complex network switch with hundreds of 112G PAM4 long-reach (LR) lanes. GUC cited a 5X boost in simulation performance and also used the Cadence IC Packaging design and analysis solution, including Allegro Package Designer Plus for implementation.

Numbers
Cadence reported financial results for the first quarter 2021 with revenue of $736 million, up 19.1% from $618 million for the same period in 2020. On a GAAP basis, income for Q1 2021 was $0.67 per share, up 52.3% from $0.44 per share in Q1 2020, with an operating margin of 28%. Non-GAAP income was $0.83 per share, up 38.3% from $0.60 per share in the same quarter last year, with an operating margin of 38%. John Wall, senior vice president and CFO, said, “We are raising our outlook for revenue, non-GAAP operating margin and non-GAAP earnings for the year while we continue to invest in our expanding multiphysics platform.”

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

May will kick off with Women in Semiconductors on May 3. Infineon’s Virtual Power Conference will take place May 4-6, followed by the 29th IEEE International Symposium On Field-Programmable Custom Computing Machines on May 9-12. The 2021 ESD Alliance CEO Outlook will take place May 18. The 2021 Embedded Vision Summit will be held May 25-28.