Week In Review: Design, Low Power

Siemens Digital Industries Software acquired Pro Design’s proFPGA product family of FPGA desktop prototyping technologies. Through a prior OEM relationship, proFPGA technology is already part of the Xcelerator portfolio; Siemens noted that the acquisition will allow for fuller integration with its Veloce hardware-assisted verification system. Pro Design will continue to operate as an independent company and a provider of electronic engineering and manufacturing services, offering consulting, development, layout and prototyping as well as volume production services, with a focus on FPGA-based solutions and PCIe boards for high-performance computing applications. “This transaction allows Pro Design to remain focused on continuing to invest in and serve its E²MS business customers to the fullest extent, while allowing the proFPGA product family to grow in line with the expanded presence that Siemens has in the EDA market,” said Gunnar Scholl, director of proFPGA Solutions, Siemens Digital Industries Software. Terms of the deal were not disclosed.

Xilinx acquired Silexica, a provider of C/C++ programming and analysis tools for FPGAs. The company’s tool suite tackles non-synthesizable and non-hardware aware C/C++ code, detects application parallelism, inserts pragmas, and determines optimal software and hardware partitioning. “Silexica’s vision is to create a disruptive developer tool – one that closes the gap between the software and hardware developer domains,” said Maximilian Odendahl, former CEO of Silexica. “The integration of our technology with the Xilinx Vitis portfolio fully aligns with our goal of making adaptive computing accessible to software developers. We are excited to continue the journey as part of the Xilinx Vitis team.” Silexica was spun out of RWTH Aachen University in 2014 and was based in Cologne, Germany. Terms of the deal were not disclosed.

Synopsys acquired Code Dx, a provider of an application security risk management solution that automates and accelerates the discovery, prioritization, and remediation of software vulnerabilities. Customers can use Code Dx’s offering in conjunction with Synopsys products immediately, thanks to pre-existing integrations as part of a partner program. “Code Dx enables our customers to optimize and harness the breadth of our application security portfolio, along with third-party tools, by aggregating, correlating, and prioritizing security testing results based on risk,” said Jason Schmitt, general manager of the Synopsys Software Integrity Group, A spin out from Applied Visions in 2015, it was based in Northport, N.Y. Terms of the deal were not disclosed.

Tools & IP
Cadence unveiled its Allegro X Design Platform, an engineering platform for system design that unifies schematic, layout, analysis, design collaboration, and data management across multiple domains, including electromagnetic (EM), thermal, signal and power integrity (SI/PI), and logical/physical implementation. “Engineers now have a framework for logical and physical design, in 2D or 3D, single- or multi-board, that allows them to optimize resources even on the most complex 5G designs, enabled by interoperability with the AWR Microwave Office RF design flow,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence.

Black Sesame Technologies licensed Arteris IP’s FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package for use in its ISO 26262-compliant automotive advanced driver assistance systems (ADAS) chips. The company had used them in a previous generation product as well.

Sequans Communications utilized Cadence’s Virtuoso RF Solution for high-frequency RF harmonic balance and electromagnetic (EM) analysis and signoff in developing its next-generation 5G IoT platform. Sequans also used the Cadence AWR Visual System Simulator software to predict and measure overall system performance and functionality.

Andes Technology uncorked AndesBoardFarm, a collection of on-line accessible FPGA boards and management software for SoC designers to evaluate and try out software on AndesCore RISC-V processors remotely.

AI
Xilinx introduced the Versal AI Edge series of adaptive accelerator SoCs targeted at edge and endpoint applications including automotive, robotics, healthcare, and aerospace. The company said that Versal AI Edge devices provide 10X compute density versus Zynq UltraScale+ MPSoCs, support multiple safety standards, and integrate new accelerator RAM with an enhanced memory hierarchy for evolving AI algorithms to provide improved AI performance-per-watt with lower latency.

Researchers from Google report using deep reinforcement learning for chip floorplanning. “In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area,” the researchers said in a new paper. The method uses an edge-based graph convolutional neural network architecture capable of utilizing past experience to speed solving problems. The team used the approach to design the next generation of Google’s AI accelerators.

Quantum computing
Honeywell Quantum Solutions (HQS) and Cambridge Quantum Computing (CQC) will combine to form a new, standalone business. The new company will offer a trapped ion-based quantum computer and a full suite of quantum software, including quantum operating system. CQC’s software business will remain hardware agnostic and be fully compatible with all global quantum hardware providers. Honeywell will own a majority stake in the company and will also invest between $270 million and $300 million in the new company alongside a long-term agreement to help manufacture the critical ion traps needed to power the quantum hardware. Honeywell formed its quantum business in 2018; CQC was founded in 2014 and had raised over $67M, with Honeywell one of its investors. The combination is expected to be complete in the third quarter of 2021.

The Quantum Technology and Application Consortium (QUTAC) is a newly founded consortium with the goal  of further developing the existing fundamentals of quantum computing into usable industrial applications. Founded by ten German companies, BASF, BMW Group, Boehringer Ingelheim, Bosch, Infineon, Merck, Munich Re, SAP, Siemens, and Volkswagen, it is specifically focused on bringing to market maturity applications for the technology, chemical and pharmaceutical, insurance and automotive industries. “In the Stimulus and Future Package, the German Government has given a big boost to the development of Quantum Computers. Working together with companies and start-ups we will identify, develop, trial, and share applications. There are many highly interesting areas, e.g., in logistics, transport, chemicals and the financial sector,” said Peter Altmaier, Federal Minister for Economic Affairs and Energy.

The Hartree Centre (part of the UK Research and Innovation’s Science and Technology Facilities Council) and IBM are forming a five year, £210 million (~$298M) partnership with the aim of applying AI, high performance computing, data analytics, quantum computing, and cloud technologies to accelerate solutions to industry challenges including materials development, life sciences, environmental sustainability, and manufacturing.

Standards
NVM Express published the NVMe 2.0 family of specifications, which aims to support faster and simpler development of NVMe solutions, including for enterprise and client solid state drives (SSDs), removable cards, compute accelerators and HDDs. New features include a zoned storage device interface that allows the SSD and host to collaborate on data placement, KV Command Set to provide access to data on an NVMe SSD controller using a key rather than a block address, and a mechanism to allow an NVMe SSD controller to support the different command sets that are defined as part of the NVMe 2.0 release as well as a path for future command sets.

Upcoming event: June 24, Rambus Design Summit, focused on IP solutions for the data center, 5G/edge and IoT devices, including accelerating and securing AI/ML applications. Critical enabling IP including HBM2E, GDDR6, PCIe 5.0 and MIPI interfaces as well as Root of Trust and network security protocol engines will be covered. Steven Woo, a Rambus fellow, will keynote the conference with an exploration of technologies that will shape the future evolution of the data center. On June 24, Ed Sperling, Semiconductor Engineering‘s editor in chief, will moderate a panel on the future of the data center.