Week In Review: Design, Low Power

Rambus is making a push for Compute Express Link (CXL) with two acquisitions and the launch of its CXL Memory Interconnect Initiative. The initiative aims to define and develop semiconductor solutions for advanced data center architectures, with initial research and development focusing on solutions to support key memory expansion and pooling use cases.

CXL is an open interconnect specification for CPU-to-Device and CPU-to-Memory designed to improve data center performance. It maintains memory coherency between the CPU memory space and memory on attached devices.

“We are in the midst of a generational shift in data center, and PCI Express and CXL are the backbone of future architectures,” said Luc Seraphin, president and CEO of Rambus, adding that the initiative is highly complementary to the company’s existing server DIMM chipset business.

As part of the effort, Rambus is planning to acquire two other connectivity IP companies, PLDA and AnalogX.

PLDA provides high-speed interconnect IP supporting multi-gigabit rates and protocols including CXL, PCIe, and CCIX. The acquisition will add CXL 2.0, PCIe 5.0 and PCIe 6.0 controller and switch IP to the Rambus portfolio and accelerate the time to market for complete CXL interface subsystems, as well as providing critical building blocks for the new initiative. “PLDA’s industry-leading digital IP ideally complements the Rambus product offering and this acquisition will augment our combined market opportunity,” said Arnaud Schleich, co-founder and CEO of PLDA. PLDA was founded in 1996.

AnalogX offers low power multi-standard connectivity SerDes IP solutions. The acquisition will add SerDes technology specifically built for ultra-low power and very low latency to Rambus’ family of PCIe 5.0 and 32G Multi-protocol PHYs. “The industry-leading PHYs and DSP design expertise from AnalogX will feed our roadmap for data center interconnect chips and expand our reach to new applications across data center, AI/ML, and 5G,” added Seraphin. Based in Toronto, Canada, AnalogX was founded in 2017.

Both acquisitions are expected to close in the third calendar quarter of 2021. Terms of the deals were not disclosed.

Tools
Diakopto emerged from stealth with a new EDA software tool and methodology to identify and analyze critical parasitic elements responsible for bottlenecks, choke points, and weak areas. The company says its tool can reduce parasitics-related IC debugging and optimization time from days or weeks to minutes or hours and can be used on a broad range of designs. “A new methodology and new breed of insightful, intuitive tools that treat parasitics as a first-order design parameter are needed to help semiconductor companies more effectively adapt to this new reality where interconnect parasitics are more important than transistors, and when the layout is now the circuit,” said Maxim Ershov, Diakopto co-founder, CEO and CTO.

Ansys’ Redhawk-SC and Totem power integrity platforms were certified for TSMC’s N3 and N4 process technologies, including for power network extraction, power integrity and reliability, signal electromigration (EM), thermal reliability analysis for self-heat, thermal-aware EM, and statistical EM budgeting.

CEA-Leti and Siemens Digital Industries Software collaborated on an updated process design kit (PDK) that allows photonic designers to select multiple methodologies compliant with the Calibre physical verification platform, including layout centric, schematic driven, and layout automation, and provides access to CEA-Leti’s 300mm photonics multi-project wafers. The PDK is also compatible with Siemens’ Tanner L-Edit software for photonic design and waveguide creation as well as the LightSuite Photonic Compiler.

JEDEC established JEP181, a neutral file, XML-based standard aimed at simplifying thermal model data sharing between suppliers and end-users in a single file format called ECXML (Electronics Cooling eXtensible Markup Language). “The JEP181 standard from JEDEC benefits thermal design engineers by providing wider availability of the key data necessary to validate the thermal performance of today’s advanced designs,” stated Ghislain Kaiser, senior director, Intel Corp. “This standardized format will allow more interoperability between engineering teams, leading to substantial time and cost savings by removing design barriers previously common in thermal engineering.” JEP181 was proposed and chaied by Siemens Digital Industries Software.

IP
Cadence unveiled the Tensilica FloatingPoint DSP family. Aiming to provides a scalable and configurable solution designed specifically for floating-point-centric workloads, the four new DSP IP cores extend from small, ultra-low power to very high performance for a broad array of applications. Cadence said that the new FloatingPoint DSPs deliver a 25% improvement in fused multiply-add (FMA) operations compared to Tensilica fixed-point DSPs with the vector floating-point unit (VFPU) add-on and offer up to 40% area savings compared to the similar class of fixed-point DSPs with VFPUs. Software tools provide auto-vectorization that helps optimize the scalar code to utilize the vector floating-point units.

“Floating-point numbers are used widely in modern computations across a broad range of compute-intensive applications, and the need for floating-point processing is growing,” said Larry Przywara, senior group director, Tensilica marketing at Cadence. “Energy-efficient, cost-effective and high-performance DSPs designed specifically for floating-point-centric computation are critical for developing competitive and differentiated products.”

Arm is providing optimized physical IP and implementations, Arm POP IP, for TSMC 3nm process technology. The physical IP is designed for high and low voltage tolerance, logic libraries with high-drive cells, technology files supporting aggressive via pillars or ladders, as well as high sigma timing sign-off using LVF. Early 3nm logic library and memory evaluation kits are also available. Arm added that a partner recently taped-out a test chip, validating Armv9 physical IP on TSMC 3nm.

Precise-ITC released Ethernet IP core optimized for AI/ML applications. It supports a single channel of 800GE or a combination of lower rates of 100GE, 200GE, and 400GE, as well as Physical Coding Sublayer (PCS) for 64B/66B, type 800GBASE-R function based on the IEEE 802.3bs/cd, FEC, and MAC layer functions.

If the Nvidia acquisition of Arm is blocked by regulators, incoming Qualcomm CEO Cristiano Amon expressed interest in investing in the company should SoftBank choose to list it as a public company, according to a CNBC report. “If Arm has an independent future, I think you will find there is a lot of interest from a lot of the companies within the ecosystem, including Qualcomm, to invest in Arm,” Amon said. “If it moves out of SoftBank and it goes into a process of becoming a publicly-traded company, [with] a consortium of companies that invest, including many of its customers, I think those are great possibilities.”

Power
Infineon Technologies expanded its EiceDRIVER product portfolio of three-phase gate driver ICs with 6EDL7141, a fully programmable solution for advanced motor control applications. Packaged in a 48-pin VQFN with a 7×7 mm² footprint, it features an SPI interface for gate drive outputs configuration, as well as an integrated power supply and dual charge pumps to supply all system functions.

Memory
sureCore and Intrinsic are teaming up on embedded RRAM that leverages Intrinsic’s CMOS compatible technology and sureCore’s high-performance, low power memory architectures. The companies said the RRAM technology requires no modifications to FEOL processing and can be readily integrated in a standard BEOL metal stack, significantly easing foundry deployment. Key markets include MCUs, IoT, and edge AI.

Market research firm IC Insights is raising its 2021 forecast, now expecting a 24% growth for the worldwide IC market. Strong per-bit pricing in the DRAM and NAND flash markets along with an improved outlook for logic and analog ICs drove the forecast increase, with every major general-purpose analog and application-specific analog market segment tracked expected to post a double-digit increase in 2021.

HPC & data center
Cortus is developing a high-performance RISC-V Out-of-Order (OoO) processor core for the European eProcessor project, which aims to create an open-source full stack ecosystem for high performance computing workloads. The processor includes full cache coherency to enable large scale systems with a very large numbers of processors for a full-scale supercomputer.

Intel uncorked plans for its infrastructure processing unit (IPU), a programmable networking device designed to enable cloud and communication service providers to reduce overhead and free up performance for CPUs. Intel says IPUs could enable a shift to a fully virtualized storage and network architecture where a cloud provider can securely manage infrastructure functions while enabling its customer to entirely control the functions of the CPU and system memory.

Quantum computing
IQM Quantum Computers released an open-source software tool to automate the design of superconducting quantum processors. KQCircuits, a Python library jointly developed by Aalto University and IQM using the KLayout design program, can generate multi-layer two-dimensional-geometries representing common structures in quantum processing units. It also allows designers to check signal routing before fabrication.

Toshiba Europe’s Cambridge Research Laboratory demonstrated quantum communications over optical fibers exceeding 600 km in length, a record. The researchers said such a distance could enable quantum-secured information transfer between metropolitan areas and a global network of quantum computers. The demonstration relied on a ‘dual band’ stabilization technique that sends two optical reference signals at different wavelengths that help protect the fragile quantum information.

Fraunhofer-Gesellschaft deployed an IBM Quantum System One, the first outside of IBM. Powered by a 27-qubit Falcon processor, the first projects the system will be used to investigate include new simulation approaches for materials in energy storage systems, financial asset portfolio optimization, and improving stability parameters in energy supply infrastructures.