Altair buys Concept Engineering; AMD’s roadmap; RISC-V GPUs; TSMC certifications.
Altair, a provider of software and cloud services for CAE, HPC, simulation, and data analysis, acquired Concept Engineering, a provider of automatic schematic generation tools, electronic circuit and wire harness visualization platforms that provide on-the-fly visual rendering, and electronic design debug solutions. “Concept Engineering’s advanced, reactive visualization technology is a best-in-class solution to help organizations accelerate their designs that have specific design architecture requirements, as well as rigorous service needs,” said James R. Scapa, founder and chief executive officer, Altair. “Integrating this technology into our electronic system design suite will offer our customers comprehensive and fast visual representations of complex system models and debug capabilities for electronic systems.” Founded in 1990, Concept Engineering is based in Freiburg, Germany. Terms of the deal were not disclosed.
Allegro DVT, a provider of video codec compliance test suites and semiconductor video IP, acquired Labwise, a provider of digital TV test services to TV OEMs, digital TV broadcasters, and operators. “This acquisition is a natural addition to our video compliance streams solutions and will allow us to extend our business and include testing services,” said Nouar Hamze, CEO of Allegro DVT. Labwise was founded in 2004 and is based in Tampere, Finland. Terms of the deal were not disclosed.
AMD detailed its latest multi-generational CPU core, graphics, and adaptive computing architecture roadmaps. Among the announcements is AMD XDNA IP, which will be integrated into multiple products and includes a Xilinx FPGA fabric that combines an adaptive interconnect with FPGA logic and local memory along with its AI Engine that provides a dataflow architecture optimized for high performance and energy efficient AI and signal processing applications. The Xilinx AI Engine will also be incorporated into the Ryzen, EPYC, and Xilinx Versal products for small and mid-size AI models.
AMD also announced several future data center products, including the Instinct MI300 AI accelerators, which it expects to deliver a greater than 8x increase in AI training performance compared to the Instinct MI200 accelerator and use a 3D chiplet design combining AMD CDNA 3 GPU, Zen 4 CPU, cache memory, and HBM chiplets. AMD will also be changing its financial reporting segments, dividing them into data center, embedded, client, and gaming.
Think Silicon debuted RISC-V-based GPUs. Available in two series for graphics and AI acceleration, the NEOX GPU IPs offers programable compute shaders running on a real-time operating system, supported by light-weight graphics and machine learning frameworks. They target applications such as smartwatches, AR, surveillance, and POS displays. The company also introduced a multi-core, vector and 2.5D raster graphics GPU for displays in battery-driven, power-constrained products.
Alphawave IP added two new interconnect IPs. The first is a is a die-to-die parallel interface for chiplets that supports emerging standards, such as Universal Chip Interconnect Express (UCIe), Bunch of Wires (BOW), Open High Bandwidth Interconnect (OpenHBI), and others. The second is a 112Gbps PAM4 optical SerDes that enables direct drive of optics and includes advanced DSP techniques for receiving optical waveforms. They are available for TSMC N5 and N4 processes.
Cadence’s digital and custom/analog design flows were certified for the TSMC N3E and N4P processes, supporting the latest design rule manual (DRM). In addition, Cadence and TSMC delivered N3E and N4P process design kits (PDKs) and design flows to accelerate mobile, AI, and hyperscale computing design. Cadence also announced that its RFIC solutions are enabled to support TSMC’s N6RF Design Reference Flow and PDK.
Siemens’ Aprisa digital implementation solution was certified by TSMC for its N5 and N4 process technologies. Additionally, Siemens’ Calibre nmPlatform physical verification solution and the Analog FastSPICE platform for verification of analog, RF, mixed-signal, memory, and custom digital circuits were certified for TSMC’s N4P and N3E processes. As part of the custom design reference flow (CDRF) for TSMC’s N3E process, the Analog FastSPICE platform supports Reliability Aware Simulation, which includes aging, real-time self-heating effect and advanced reliability features.
Synopsys’ digital and custom design flows were certified for the TSMC N3E and N4P process technologies. In addition, Synopsys’ Foundation IP and Interface IP are available now on the N3E and N4P processes. The digital and custom design flows and IP are based on the latest versions of TSMC’s design rule manual (DRM) and process design kits (PDKs). Synopsys also introduced a new RF design flow developed with Ansys and Keysight for the TSMC N6RF process.
QuickLogic and eTopus collaborated on a disaggregated eFPGA-enabled chiplet template solution. Initially available as configurable IP and eventually as chiplets, the first template will use 6nm process technology with LUT counts starting at 200K and additional functionality available in block RAM and DSP blocks, surrounded by up to 384 Die2Die links that can run at 0.5/4/8/16G. It will support emerging industry chiplet interfaces including the Bunch of Wires (BOW) and Universal Chiplet Interconnect Express (UCIe) standards.
Real Intent updated its clock domain crossing sign-off tool, adding complete, flat, and hierarchical sign-off; multimode-aware dynamic CDC models; and CDC analysis enhancements for low noise sign-off, including handshake and interface handling, glitch detection, and reconvergence. It also added new features to its RTL linting sign-off tool, including four user-customizable severity levels, results filtering by file or design module, violation sorting and grouping, and keyword searching.
Avery Design Systems added support for the Universal Chiplet Interconnect Express (UCIe) die-to-die interconnect standard in its pre-silicon verification models and test suites. It includes support for standalone UCIe die to die adapter and LogPHY verification along with integrated PCIe and CXL VIP to run over the UCIe stack.
Infineon expanded its Bluetooth portfolio, adding a new Bluetooth & Bluetooth Low Energy (LE) SoC compliant with Bluetooth 5.2 and designed for IoT applications including medical, home automation, security, and industrial. The SoC is also available in three modules that also include onboard crystal oscillator and passive components.
Renesas Electronics announced two development kits for IoT cloud products for its RA and RX 32-bit MCU families. Using Renesas’ RYZ014A Cat-M1 LTE cellular module, the cloud kits connect wirelessly between MCUs and cloud services without a gateway. They also include multiple sensors, a high-performance MCU, hardware-based security, and software stack.
NXP uncorked a new line of microcontrollers. The Arm Cortex-M core-based portfolio includes four series focused on high-performance, cost-optimized and analog, low-power wireless connectivity, and ultra-low power. A development tool suite is also available.
IAR Systems updated its embedded development toolchain for Arm, adding support for the Cortex-M85 processor.
The MCU market in 2021 was dominated by five companies that accounted for 82.1% of worldwide MCU sales, market research firm IC Insights reported. NXP, Microchip Technology, Renesas, STMicroelectronics, and Infineon made up the top five companies, with market shares ranging from 18.8% to 11.8%. MCU sales in 2021 saw a 27% increase to a record-high $20.2 billion, according to the firm.
D-Wave debuted the experimental prototype of its next-generation annealing quantum computer. The Advantage2 prototype has 500+ qubits, with 20-way inter-qubit connectivity. The company said that early benchmarks showed more compact embeddings, lowered error rates, and improved solution quality and increased probability of finding optimal solutions. It is scheduled to be available in 2023-2024.
Quantinuum upgraded its H1-1 quantum computer, expanding to 20 fully connected qubits and increasing the number of quantum operations that can be completed in parallel. JPMorgan Chase has been testing the quantum computer, said Marco Pistoia, distinguished engineer and head of quantum computing and communication research in the bank. “In our experiments, we used the 20 qubits of the H1-1 computer on a quantum Natural Language Processing algorithm for extractive text summarization. The results were almost identical to the reference values computed with a noiseless simulator, validating the computer’s high fidelity, as shown in our recent arXiv preprint.”
Renesas Electronics developed circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM) test chip with fast read and write operations fabricated using a 22 nm process. The test chip includes a 32Mbit embedded MRAM memory cell array and achieves 5.9-nanosecond random read access at a maximum junction temperature of 150°C, and a write throughput of 5.8 MB/s. Key to the test chip, Renesas said, is “a new technology utilizing capacitive coupling to boost the voltage level of the differential input nodes, allowing the differential amplifier to sense a voltage difference even when the memory cell current difference is small, achieving high-precision and fast read operation.”
Imec recently presented a scalable neural readout microchip featuring one of the world’s smallest recording channels for the simultaneous acquisition of local field potentials and action potentials in neurophysiology experiments. The chip is based on a novel AC-coupled 1st order delta-delta-sigma (Δ-ΔΣ) architecture that enables the conversion to the digital domain very close to the weak analog signal source. “This scalable digitally-intensive design ensures a small footprint and low-power IC with good performance for the concurrent acquisition of neural signals. It’s opening the way towards even smaller probes with higher electrode densities that would drive neuroscientific research forward,” said Carolina Mora Lopez, team leader of the Circuits for Neural Interfaces Team, Imec.
DARPA launched a new project to enable recovery of rare earth elements from e-waste. The Recycling at the Point of Disposal (RPOD) program is made up of several university teams that will develop new extraction chemistries and explore practical limits of yield, extraction efficiency, and purity to recover up to seven critical elements from a feedstock representative of commercial and Department of Defense e-waste. The technology for both separation and coextraction of critical elements will ultimately be demonstrated in a benchtop hardware prototype.
Read more of the week’s news at Manufacturing, Test and Auto, Security, Pervasive Computing.
Find out if analog can make a comeback in the latest Low Power-High Performance newsletter. Plus, read why thermal issues in DRAM are reaching a crisis point and whether the IP industry is ready to undergo a transformation. The latest Systems & Design newsletter digs into processor optimization, a possible silver lining in the semi talent crunch, disaggregation, whether AI-powered verification will solve anything, chiplet benefits, and embedded software complexity.
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