Week In Review: Design, Low Power

Synopsys completed its acquisition of QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Terms of the deal were not disclosed.

Synopsys launched the PrimeECO design closure solution, a signoff-driven solution that the company says achieves signoff closure with zero iterations. The tool includes a machine-learning-driven Hybrid Timing View with compute resource prediction and management, a common data model with Fusion Design Platform, and a graphical user interface for design visualization with exclusive signoff timing overlay and available plug-ins for user-driven optimization. It will be available in December.

Mentor debuted the final phase of the Valor software NPI DFM technology for automated PCB design reviews, adding assembly DFM checks to the new process flow and enabling critical design data to be automatically extracted to derive PCB technology classifications for appropriate manufacturing process constraints. It works with all major PCB layout tools.

Xilinx unveiled Vitis, a unified software platform to automatically tailor the Xilinx hardware architecture to the software or algorithmic code without the need for hardware expertise. The platform plugs into common software developer tools and utilizes a set of optimized open source libraries. The Vivado suite will remain separate for those who want to program using hardware code.

Lattice Semiconductor uncorked a new FPGA family for MIPI D-PHY based embedded vision systems. The small, low power CrossLinkPlus family features integrated flash memory, a hardened MIPI D-PHY and high-speed I/Os for instant-on panel display performance, and flexible on-device programming capabilities. Also available are ready-to-use IPs and reference designs for implementation of enhanced sensor and display bridging, aggregation, and splitting functionality.

SmartDV added support for the Verilator free and open-source hardware description language (HDL) simulator to its portfolio of standard and custom protocol VIP. Verilator compiles synthesizable SystemVerilog and synthesis assertions into single- or multithreaded C++ or SystemC code and is designed for large projects with fast simulation performance requirements.

Sofics expanded its electrostatic discharge (ESD) protection and pre-silicon analog I/O portfolio to support TSMC’s N5 process technology.

Cadence and Adesto are teaming up to expand the ecosystem around the Expanded Serial Peripheral Interface (xSPI) communication protocol to enable higher transfer rates and lower latency for flash memory in IoT devices. The new Cadence Memory Model for xSPI allows optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI non-volatile memory (NVM).

Additionally, Adesto joined the Microsoft Azure Certified for IoT program, enabling hardware and software that has been pre-tested and verified to work with Microsoft Azure IoT services.

ANSYS added a new licensing model for its simulation tool suite. Elastic Licensing provides flexibility when additional resources are needed for a limited period or on an occasional basis for both on-premise use and internet-based usage monitoring. It can be used as a stand-alone option or it can be combined with other existing licenses.

The Gen-Z Consortium published the Gen-Z Physical Layer Specification 1.1. Updates include enhanced support for PCIe Gen5 and support for Gen-Z 50G Fabric and Local Physical Layers. PCIe Gen5 doubles the link bandwidth from PCIe Gen4’s 16GT/s to 32GT/s per lane. Likewise, Gen-Z 50G doubles the link bandwidth of Gen-Z 25G through Four-level Pulse Amplitude Modulation (PAM4) and adds ultra-low-latency Forward Error Correction (FEC) for improved link reliability.

Automotive supplier NSITEXE selected UltraSoC’s embedded analytics technologies for use in future autonomous vehicle designs, citing the enablement of monitoring and reporting.

People & Events
Dr. Mary Jane Irwin is the 2019 recipient of the Phil Kaufman Award. Irwin is the Evan Pugh Professor and A. Robert Noll Chair Emeritus in Engineering in the Department of Computer Science and Engineering at Pennsylvania State University and was selected for her extensive contributions to EDA through her technical efforts which included creating EDA tools then using them in computer architecture research, service to the community, and leadership. “Dr. Irwin has had a tremendous impact on education, particularly VLSI systems design, computer arithmetic, EDA and low-power computer architecture,” said Dr. David Atienza, president of IEEE-CEDA and professor of Electrical Engineering at EPFL. “Her course materials and textbooks have been used around the world to train numerous electrical and computer engineers who have become leaders in key IC and EDA companies such as Intel, AMD, Cadence and Mentor.” Irwin was the chair of DAC in 1999 and received the Marie R. Pistilli Women in EDA award in 2004. A celebration and dinner will be held Nov. 7 from 6:30 p.m. until 9:30 p.m. at The GlassHouse in San Jose, CA, hosted by the ESD Alliance and IEEE CEDA.

DAC, which will be held July 19-23 2020 in San Francisco, opened submissions on design research, design practices and design automation for the Research Track, Designer Track and IP Track. The research track abstracts deadline is November 27, 2019. The Designer Track, Embedded Track, and IP Track presentation submission deadline is January 22, 2020.

Check out upcoming industry events and conferences: Arm TechCon will take place Oct. 8-10 at the San Jose, CA Convention Center. Also on Oct. 10 is the PCB Systems Forum 2019 – Milan in Milan, Italy. Later in the month, the System-on-Chip Conference will be at the University of California, Irvine on Oct. 16-17, while the 13th IEEE/ACM International Symposium on Networks-on-Chip will be held Oct. 17-18 in New York, NY.