Week In Review: Design, Low Power

Video codec acquisition; automotive flow; Samsung MDI support.


Allegro DVT acquired Amphion Semiconductor, bringing together two developers of video codec IP. Allegro DVT said the merger will make it the first semiconductor IP company to offer commercially available hardware-based, real-time encoder and decoder solutions for the new AV1 video encoding format for SoC implementations, supporting 4K/UHD up to 8K. Based in Belfast, Northern Ireland, Amphion was founded in 1994. In 2004, the company was acquired by Conexant. It was re-restablished in 2015 following a managmenet buyout of its IP.

Amphion CEO Stephen Farson commented, “Through working together in servicing our shared customers, the Allegro DVT and Amphion teams have already shown not only a similarity in our approaches to video codec design, but an ability to work closely together as separate companies. The combined company will allow us to accelerate and enhance our product development and further elevate the excellence in the solutions we deliver to our customers.”

Synopsys announced native automotive solutions as part of a complete digital design flow incorporating functional safety-enabled technologies, allowing generation of functional safety intent early in the design flow to describe safety mechanism behavior, which is used as input and maintained throughout the digital design flow. FuSa mechanisms needed to meet particular ASILs include including triple-mode redundancy (TMR), dual-core lock-step (DCLS), and failsafe finite state machine (FSM). NXP plans to deploy the automotive design solution on its next-generation safety-critical SoCs, and said the solution for implementing TMR registers reduced IC Compiler II placement and legalization runtime by more than 20 percent on its 16nm S32G274 automotive network processing chip.

sureCore’s PowerMiser low power SRAM IP is now available for designs targeting the Samsung 28nm FDS process. At the 28FDS process node, the single port PowerMiser supports an operating voltage range from 0.7V to 1.2V and provides 50% dynamic and 20% leakage power savings over competitors, according to the company.

ANSYS’ multiphysics simulation tools for power, signal and thermal integrity and reliability analyses have been certified for Samsung Foundry’s latest multi-die integration (MDI) 2.5D/3D-IC packaging technology. The certification allows for detailed modeling of silicon interposer, through silicon vias, microbumps, high-bandwidth memory, high-speed interfaces and different dies.

Cadence’s custom and analog/mixed signal design flow has been certified for Samsung Foundry’s 5nm Low-Power Early (5LPE) process technology. Additionally, a process design kit (PDK) techfile is now Mixed-Signal Open Access-ready for the Virtuoso-Innovus Implementation System flow. Additionally, Cadence’s 3D-IC advanced packaging flow was certified for Samsung Foundry MDI packaging based on the 7nm Low Power Plus (7LPP) process. It provides a full planning, implementation and analysis flow for 3D multi-die packages. Cadence’s automotive reference flow was also certified by Samsung for advanced-node automotive designs. The flow was validated on Samsung Foundry 8nm Low-Power Plus (8LPP) process.

Synopsys’ Fusion Design Platform and Custom Design Platform now support Samsung’s 2.5D-IC MDI on the 7nm Low Power Plus (7LPP) process as well as the SUB20LPIN silicon interposer. They include automated silicon interposer creation and routing, place and route among microbumps, TSVs, and C4 bumps, and auto SPICE deck generation for power and signal integrity analysis of HBM and high-speed interface channels. Synopsys also worked with Samsung on an automotive reference flow based on its 8LPP process to meet target ASILs for safety-critical designs. The flow includes complex functional safety analysis, implementation, and verification capabilities.

SEAKR Engineering, a provider of advanced electronics for space applications, selected Rambus’ 28G Multi-protocol long reach (LR) SerDes PHY and the CryptoManager Root of Trust for its next-generation ASIC and FPGA designs. SEAKR cited state-of-the-art performance in both moving and securing data.

Check out upcoming industry events and conferences: The CASPA 2019 Annual Conference & Dinner will highlight “AI: From Silicon to Software” on Oct. 19, 12 p.m. -9:30 p.m. in Newark, CA. The AI World Conference is scheduled for Oct. 23-25 in Boston, MA, while the Linley Fall Processor Conference will take place Oct. 23-24 in Santa Clara, CA. Finishing out the month, DVCon Europe will be hosted in Munich, Germany on Oct. 30-31.

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