Week In Review: System-Level Design

Cadence beefs up verification platform; Mentor adds security capability to car infotainment; Arteris adds team support for IP; Intel grows in data center, down slightly in PCs.


Cadence rolled out a new version of its functional verification platform, greatly improving performance and updating it to deal with the big increases in third-party and re-used IP in designs. For IP and block verification, the company said it increased formal analysis performance by up to 20% and simulation by up to 10 times. The debugger also reduces the database size by 10 times and the time needed for test bench code by 30%. On SoC verification, SoC reset and low-power simulations run 5 times faster, and mixed signal simulation runs up to 100 times faster. Full details are here.

Mentor Graphics updated its platform for Linux-based in-vehicle infotainment. The new version is compliant with the GENIVI 5.0 standard. Combined with Mentor’s type-1 hypervisor, the platform can keep critical information separate and secure.

Arteris expanded its network on chip IP to allow multiple teams to divide up the work, then reassemble it into a cohesive SoC using a low-latency protocol. The company is targeting the derivative and subsystem markets with the new capabilities.

Intel reported its annual numbers for 2013, turning in revenue of $52.6 billion and net income of $9.6 billion, down 1% from $53.3 billion in 2012 and $11 billion in net income. The company showed strength in the data center, but lost 4% in revenue in the PC client group.

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