What’s After 7nm?

The rollout of 10/7nm was a long time coming, and for good reason. It’s hard stuff, and chipmakers have to be ready to take a giant step forward with new processes, tools, and to deal with a slew of physical effects that no longer can be handled by just guard-banding a design.

The big question is what’s next, when it will happen, and how much it will cost. Preparing for the next process node is no longer an automatic progression. It takes time, equipment, and it requires dealing with an ever-expanding list of new issues.

It’s important to clarify who’s defining node numbers, too. The 7nm node introduced by TSMC and Samsung is roughly the equivalent of 10nm as defined by Intel and GlobalFoundries. Each new node represents roughly a doubling of transistors.

The confusion doesn’t stop there, either. Along with different numbering schemes, there is debate about what is a full node and what is a half-node. The full nodes, in theory, provide twice the density and better opportunities for scaling power and performance, but the half-nodes are easier to implement. Foundries have had a tough time selling the half-nodes lately, because for all but the highest-volume chips, there isn’t enough incentive to deal with the pain of that transition. This is why 20nm was considered an outright failure by most chipmakers, but it was also one of the highest-volume nodes because Samsung and Apple needed the improved density for the respective mobile devices.

There is no question that the next full node will be much more difficult for single-chip designs. FinFETs already are running out of steam, which means that the next nodes will likely require different technology, whether that is horizontal or vertical nanowires or nanosheets. They will require new interconnect materials, most likely cobalt, as well as ruthenium liners. And it’s possible that even EUV won’t be good enough for metal 1 and 2, so high-numerical aperture EUV technology will be needed.

But the likelihood that everything will stay on a single die at the next node, or the one after that (depending upon who’s defining the node), is diminishing. Intel, TSMC, IBM, GlobalFoundries, Samsung and UMC are all gearing up for a number of advanced packaging approaches to simplify scaling. There is a growing realization that not everything needs to scale—or at least not everything needs to scale equally. And that opens the door to much more freedom in design because the physical effects that result from shrinking wires and thinner dielectrics can be greatly alleviated with different packaging approaches.

Both Intel and Samsung have created their own bridge technologies to connect die, and virtually everyone is working on a 3D implementation that sharply reduces the area while improving throughput using through-silicon vias. This requires a significant shift in direction for manufacturing and design, because in 3D implementations the TSVs run through the center of the die rather than on the edge or outside the chip.

So far, advanced packaging is still a work in progress. Fan-outs are becoming much more common, and flip-chips have been around for some time. But the next phase will integrate packaging much more closely with the design on a mass-production basis, adding the same kinds of scaling benefits that shrinking features has provided for the past half century.

This doesn’t mean that device scaling is over. The theoretical limit for high-NA EUV and carbon nanotube FETs is somewhere around 1nm, and maybe even beyond that. But it’s unlikely that everything will be on the same die by that point. That will improve performance, decrease the amount of power required to drive signals, shorten time to market, and allow much more effective power management and noise isolation. Moreover, it will significantly lower the overall cost of design through manufacturing by once again allowing companies to deal with problems individually, rather than solving one and finding that has created an entirely new issue.