Why Multi-Die Integration Really Is On Its Way

Admit it. You’ve heard a lot about 3D IC’s for years now, and it’s starting to get old. Lots of talk but not much action, you say? Maybe it will never happen, you say? Well, perhaps it’s time to reassess the current situation, reevaluate emerging needs, and reset our “3D” paradigm for the coming multi-die imperative.

The problems associated with 3D IC (stacked die) are real and varied. First, there’s the cost (ROI) issue, which to date has limited its use to very few applications and insufficient volumes. Second, testing and effective yield issues, and uncertainties that add risk, provide an added disincentive. Third, there are remaining questions about the long-term business model and impact on the supply chain. Fourth, there are technical limiters due to a lack of interoperability in the design flow and need for enabling standards. Finally, there have been some legal/patent concerns that have further slowed down EDA tool development to fully support the 3D IC vision. A list as long as this could depress anyone.

Yet, there are some very large and powerful forces that are changing the landscape and dynamics for chip design (I will write a separate blog soon to expand on related changes ahead to design methodology and tool flows). As smartphones and tablets approach saturation points in established markets and new markets drive down margins, a new set of market opportunities are simultaneously emerging that combine these mobility platforms and large-scale “Big Data” servers with new types of connected devices. The need for continued integration will not stop, but the types of integration required will become more varied than in the past. One way to think of this is shift is the intersection of “More Than Moore” technologies with “Internet of Things” applications. From that premise, we can next evaluate the economics.

Early in my EE career, I assumed technical advancements drove change, and cared little about economics. After a few more years and an MBA, I gained deeper insight into the fundamental role economics plays in every aspect of engineering. Today, it is clear that the economics of traditional process scaling works for a shrinking set of applications. Economic forces will drive continued integration, but that does not mean five billion transistors on every chip. In the IoT era, heterogeneous integration of sensors/MEMs with digital logic, analog, RF, DRAM, Flash, and even energy harvesters will become the norm. These will not all reside on a single die.

How can I be so confident multi-die integration will happen? IDC estimates that spending on IoT technology and services will approach $9 trillion by 2020, creating demand for many billions of new chips. While the characteristics of IoT devices will vary by market area, the requirement for multiple die is a broadly common characteristic. A tidal wave of market opportunity this large will not be missed because our industry could not figure out how to design and build multi-die packages. Whether we use the term “2.5D”, “3D”, or other packaging innovations, now is the time to brace for a very real wave of change. In my next blog, I will explain recent progress in one important aspect of multi-die integration: 3D floorplanning, a.k.a. “pathfinding”.

Si2 is pleased to be exhibiting at the TSMC Open Innovation Platform Ecosystem Forum on Sept. 30, as well as at the ARM TechCon event on Oct. 1-2. More details at: http://si2.org.