Yield Enhancement By Virtual Fabrication

Using failure bin classification, yield prediction and process window optimization to identify and prevent process failures.


This paper provides an example of yield enhancement using virtual fabrication. A 6 transistors based static random access memory example on 7nm node technology was used in this case study. Yield loss caused by via contact-metal edge placement error was modeled and analyzed. The results show that yield can be enhanced from 48.4% to 99.0% through process window optimization and improved specification control. We identified high resistance failure as the top failure mode in both non-optimized and optimized process models.

Coventor Inc., a Lam Research Company, Shanghai, China: Qingpeng Wang, Yu De Chen, Jacky Huang, Wuping Liu, Ervin Joseph

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