How to maximize the value of prototyping.
I visited SNUG Silicon Valley last week. This annual Synopsys User Group event at the Santa Clara Convention Center is always a good way to get in touch with the end users of various EDA products.
I attended the technical track with experts from ARM, NVIDIA, Intel and Synopsys, who talked about their experience in accelerating software development, hardware verification and system validation leveraging prototyping. Their papers and presentations were full of tips and tricks on how to maximize the value from prototyping.
The ARM presenters——both named Peter—explained how the ever-increasing complexity and density of the latest ARM CPU and GPU cores, in addition to the continual demands for improved time-to-market, requires new, improved and innovative verification, validation and debug techniques. They highlighted how increased adoption of prototyping helped ARM to shift-left their IP verification activities and thus provide higher quality IP to their customers.
Ramanan and Sivarama, of NVIDIA, gave tips on how to optimize multi-FPGA prototypes for complex designs like their own Tegra SoC. They provided guidelines on how to leverage tool capabilities to partition designs across multiple FPGAs and how to benefit from high speed TDM (time-division multiplexing) to optimize the performance of these large-scale prototypes.
If you ever wondered how to prototype latch-based designs, the Intel presenter, laid out a step-by-step approach on how to effectively overcome some of the challenges that latch-based designs have typically imposed on FPGA-based prototyping. He went over a case study explaining how Intel was now able to prototype their Atom CPU where originally they could only use an emulator.
And Lance of Synopsys gave a tutorial outlining best practices for prototyping GPUs to enable pre-silicon software development and validation. He explained how to plan a GPU prototyping project and review the prototyping requirements, resources and timeline. He also talked about how to partition a GPU design and maximize the resulting prototype for performance.
Beyond the actual presentations, it was great to see the interaction between the presenters and the audience, most of them seasoned prototypers, as well. You could see many audience attendees feverishly taking notes during the presentations and asking follow up questions afterwards. If fact, many of the breaks turned into small group discussions on how to better partition, debug or optimize a prototype.
This is the real value of these types of user group conferences. Nothing beats learning from the actual experts. Check out the SNUG website in the coming weeks to view the proceedings from all of these presentations.