Overcoming RC In Memory Scaling

How to deal with shrinking Ohmic contact areas and increasing aspect ratios for feature deposition.


In a memory device, Ohmic contacts (semiconductor-to-metal interfaces) connect the active region and the metal wiring. To achieve rapid and maximal charge transmission across the Ohmic contact, a low-resistivity material is used. Low-resistivity Co silicide has been adopted as the industry standard for this purpose; its effectiveness relies on the deposition of a sufficiently thick layer to form a robust Ohmic contact.

As memory scaling continues, the area of the Ohmic contact shrinks approximately 70% node over node, while aspect ratios increase in the features in which the low-resistivity Co silicide must be deposited to form this contact. In 1xnm DRAM, these two factors are making it increasingly difficult to form a layer of silicide thick enough to ensure rapid, reliable transmission of an electrical charge from the active region through the contact to the upper levels of wiring, and back again. The animation below explains the concept of the Ohmic contact.

Two New Solutions to Scaling DRAM
How does Endura Cirrus Co address the silicide coverage challenge?

The Endura Cirrus HT Co PVD system addresses silicide coverage through enhancements that overcome the challenges of shrinking contact area and growing aspect ratios. Using a high-frequency RF source to produce plasma containing a much higher concentration of metal ions than is possible with other source technologies, the system achieves excellent thickness and uniformity at the bottom of high aspect ratio features. A negative voltage on the wafer guides positive metal ions into narrow holes; because so many more metal ions are available, coverage at the bottom of high aspect ratio contact holes is two or three times as thick as that obtained with current technology. Consequently, a robust Ohmic contact of silicide is formed that lowers barriers to charge transmission between metal and semiconductor layers.

How does Endura Versa XLR2 address the line resistance challenge?

DRAM cells operate in arrays of columns (bitlines) and rows (word lines). The bitline propagates an electrical charge to and from a sense amplifier to program (write) or retrieve data from (read) a given cell. The speed at which data is written to and read from a DRAM cell depends on the resistance (R in RC) of the bitline; the lower the resistance, the faster data are transferred. Resistance of a conductor depends on the scattering sites encountered by electrons as they move along the line. Impurities in the film, grain boundaries and surface roughness are some of the impediments that slow the electrons down (as explained in the animation below). The relative contribution of these impediments varies with film thickness.

The Versa XLR2 with PVD chamber addresses line resistance by depositing purer and smoother tungsten film with 10-15% lower resistivity than tungsten deposited using current technology. The new system achieves this enhanced quality by means of innovations to key hardware components, such as the source magnetron; novel process chemistry; and modulation of plasma characteristics. A scaling enabler, the lower-resistance tungsten produced by the Versa XLR2 system will extend the use of tungsten as the bitline metal in DRAM technology for 1xnm nodes.