When it comes to making tradeoffs, the choice of configurable core can provide a huge range of options in terms of scalability.
You might have seen that ARM TechCon is happening this week in Silicon Valley, with a number of product announcements from the IP giant accompanying the conference.
One of those is the A-35, which stuck out for me in terms of the range of scalability possible, among other things.
Here is a graphic that shows the range of scalability:
(Source: ARM)
During a press conference, I was able to ask Mike Muller, CTO of ARM directly how the A-35 can be so scalable but still so high performance.
He said a lot of the scalability is in fairly high level granularity: “Is it one core? Is it four core? Do you want the Neon block? Don’t you want the Neon block? You can make some of those bits quite easy.”
Muller also noted that over the years they’ve learned how to make it easy to go, ‘cut here.’ (Easy, meaning, it took years to figure this out and was a lot of effort.)
“Then, the ultimate bit is when you come to implementation: how hard do you push for clock frequency, and how much do you relax that back makes a significant difference in how large the final result is. At the top level, it’s the granular dotted lines about which functionality to leave in or where to put it,” he added.
This was no small task, and really represents the challenges that engineers across the industry face every day. Encouragingly, there are new resources being created all the time to make the task at least a bit clearer where the tradeoffs are concerned.
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