Speeding Up Analog

Experts at the table, part 3: The pain of analog; analog in the IoT; analog in the 3D stack.

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Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What follows are excerpts from that discussion. For part one, click here. For part two, click here.

SE: Where is analog really painful right now, why, and what can we do about it?

Miller: In the very deep process nodes, it’s basically trying to get things to match — there’s so much process variation, so much of these layout-dependent effects, whether it’s interconnect parasitics or any of the below the substrate — trying to get two transistors to reasonably match in those process technologies is just an absolute nightmare. What you end up doing is burning a lot of variating — you have so many dummies, and digitated structures, your transistor is about the same size it was before except now you’re paying 28nm access rates. Those all get worse as you get smaller. The variety of devices available to you are much lower. If you’re up in these ‘More Than Moore’ processes, you have a wide variety of devices available to you; you have a blend of accuracy in your passives and things like that; so many more choices.

Murphy: The funny thing is I was talking to a Stanford analog design prof and he said, ‘Yeah, it’s not easy designing at 28 but it’s absolutely doable; it’s a production mechanism right now, and you just do things differently. You have all these trimming devices, you design your ADCs in a different way, you don’t just try to take the same structure and drop it in 28nm.’ And he said people are toughing it out and getting on with it. The world is changing.

Luo: I totally agree with the variation. The other piece is a lot more modes and corners in general. But on 28, people are designing analog in 28, the challenge that is scaring people are the big consumer guys who are doing 16 and 14nm, and some at 10 — where now you’ve got FinFETs, so you’ve got a limited set of widths and lengths you can play with because you are dictated by the manufacturing process, by the foundry, what you can play with.

Hoskins: It’s becoming more digital.

Luo: Yes, exactly, so now what do you do? All of those little tuning knobs — those are not for [the analog designers].

Shuler: But for those guys, there’s been all this talk about TSVs, 3D, etc., forever — but when we look at some of our customer slides with the wedding cake of the TSV chip: there’s the digital die, there’s the analog stuff, there’s the memory stuff down there. That analog stuff is in a larger process node. Whether that will turn into reality…

Hoskins: It’s the cost effectiveness of this stuff.

Murphy: Although ASE is starting to do some stuff in putting die together, so stacking die themselves. They’ve got their own interposers and they’ll do their own assembly.

Shuler: And they are taking on the risk of getting the die from two different suppliers?

Murphy: That’s a good question; I don’t know who’s doing that.

Luo: TSMC is doing it too where now you’ve got a classic semi foundry now taking on the packaging and assembly too.

Shuler: For our customers, it’s the big guys who have a lot of technology like Samsung and Toshiba is doing some stuff, but they own so many of the moving parts it makes it easier to control it.

Murphy: The reason I mentioned ASE is I saw an interesting presentation where they showed that a lot of the IoT devices will be a stack of different die — the analog piece, the radio, the digital piece — what I got out of that was the interesting conclusion that these IoT things are not going to be SoCs in the sense that we understand them. They’re going to be 3D stacks of completely different things.

SE: What about the design tradeoffs, being that 28 is so painful — how quickly can a design team figure out what is the best way to go from a cost perspective, and given the different constraints they know they’re going to have to deal with based on the different processes?

Miller: It depends on if the analog guys get to choose. Usually, the digital needs drive that decision in the kind of SoC space we’ve been talking about here. If you’re not in the mindset, then you make a completely different set of decisions. If you’re at 28nm, you’re there because that’s where the digital team needs to be to meet their cost and other requirements, and there you are, you’re stuck with it — go make it happen.

Hoskins: I wouldn’t say we’ve seen a lot of upheaval going on from 40 to 28, for example. We’ve got some architectural reuse going from 40 to 28, so there are a lot of DFM issues, but it’s not changing our design flow alongside, and it’s not necessarily changing our architectures — it’s not fundamentally different. I don’t know if I’d say the same thing about going to FinFET or the next node beyond that but I think going to 28 at least still seems to be a node that’s in the same way of doing things for the analog designers. I don’t think we’ve seen a change of habits, really. All of the things we talked about in terms of how to integrate into the SoC and the challenges of producing all of those different views and associated stuff that the SoC needs were prevalent in 90nm as well as 65, 40 and 28. Those have been there and we just haven’t managed to still fix those analog productivity things, but I don’t think 28 necessarily brought another level of that or changed that fundamentally. That’s what I’ve been seeing over the last few years.

SE: What else architecturally can be done to speed up analog?

Hoskins: I think about reuse in a way, and reuse is something in the digital world that has made huge differences in speeding up designs because we’ve got a level of abstraction with RTL that gives us great reuse across any technology. We don’t really get that in the analog world, and then when I mention architectural reuse between nodes, we’ve had a decent amount of that — it’s often a choice, though. If we are spanning nodes with a look and feel of a similar product family, we make those choices because we want a similar look and feel also that we’re going to get some reuse architecturally, circuit-wise. So we have circuit designers working on multiple nodes concurrently doing designs that are essentially common architecturally. That does help us a lot in productivity and getting designs done quicker for sure; it might not necessarily to extracting most that you can out of a given technology but that does seem to be working from a reuse point of view. It’s become a necessity with the number of nodes and the speed at which we are moving through nodes, still. It hasn’t slowed. It wasn’t like we got to some last node and said, ‘Take a breather, guys.’



  • Kev

    One of the main problems with speeding up analog is that the analog designers and associated EDA guys are rooted in the physics and maths of their problems and are very bad at abstraction. Trying to persuade someone used to designing with transistors in schematics that they should write a behavioral model in Verilog-A is a bit of a non-starter. Likewise the EDA guys are usually lost for ways to automate the process.

    We’re actually into a 4th generation of analog design now, the first was using valves (at high Voltage), then 2) individual (unmatched) transistors, then 3) custom ICs (with matching) and now we are looking at stepping back to 2 with digital management for correcting mismatch issues etc. due to variability. Since the 4th generation expert actually requires two skill sets for their design work there’s even less chance they’ll be good at the other stuff too.

    It would look more hopeful if standards like VHDL(-A) and Verilog-AMS worked properly, but they don’t and there’s no sign of the major EDA companies fixing them (they haven’t for the last two decades).

    Can it be sped up? Yes, sure, but nobody is spending the money to do it, and some people are deliberately obstructing the process.