January 2011 - Page 3 of 3 - Semiconductor Engineering

Packaging’s Power Play

By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler In the not-too-distant past packaging was not an issue IC designers had to think much about. But now, due to smaller geometries and rising complexity, managing power in the entire system has become a major concern for system architects. IC and package designers now must work closely throughout the design process to make sure no surprises come up down the road. A... » read more

Power Next

By Barry Pangrle - 13 Jan, 2011 - Comments: 0

Development teams are faced with many tradeoffs when defining a new product: How much should it cost? What functionality or features need to be included? And what level of performance is required? As an example, in order to reduce costs it’s possible to trade away performance by implementing functionality in software instead of in application-specific hardware. For an SoC that already inc... » read more

Golden Power Intent

By Luke Lang - 13 Jan, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about the rapid adoption of the power intent file for low-power designs. While this is certainly a step in the right direction, some design teams may be taking several steps backwards by not treating the power intent file with the proper respect. For example, I have seen one case where the verification, synthesis, and backend implementation teams each had... » read more

The Challenge Of Packaging

By Ann Mutschler - 13 Jan, 2011 - Comments: 0

Semiconductor packaging isn’t a sexy subject, and it’s one that’s been largely overlooked by the design community. Until now, that is. I recently spoke with Brad Griffin at Cadence, who stressed that managing the power through packages even on a single die is still one of the most challenging things engineers must navigate. “As people integrate more technology into a single chip o... » read more

What is CPS?

By Matt Elmore - 12 Jan, 2011 - Comments: 0

CPS stands for Chip-Package-System. It represents a paradigm shift from the old partitioned approach of IC design into a cohesive methodology that considers the ecology of the system as comprised of the chip, package and board. Today’s design requirements are calling for a revisit to the way we look at IC design and validation. Companies no longer can afford to view design with a silo-base... » read more

The Elusive Min Power Definition

By Ed Sperling - 10 Jan, 2011 - Comments: 0

By Ed Sperling Put a fully charged smart phone in a bad reception area and the battery will run out in a fraction of the time it normally lasts in a good reception area. While this may be an annoyance to consumers, who need to recharge their phones more often, it’s a serious problem in SoC design. Minimum power should be a simple number, but the reality is it’s more like a distribution ... » read more

Blog Review: Jan. 5

By Ed Sperling - 05 Jan, 2011 - Comments: 0

By Ed Sperling Mentor’s Robin Bornoff returns to his beer fridge with a New Year’s resolution for sobriety and a revelation that an empty refrigerator never cools as well as a full one. Well, there’s always Diet Coke and double-shot iced espresso. Cadence’s Tom Anderson sheds some long overdue light on the famous processor “divide bug” that generated mostly right answers. This o... » read more

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