May 2011 - Page 3 of 4 - Semiconductor Engineering

Extraction, Power And Final Silicon
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor technology scales down, manufacturing effects are coming front and center, putting constant pressure on design teams to make sure that silicon can be modeled through the extraction process while performing analysis accurately. Extraction technology is one of the basic components needed to gain an accurate measurement of power, timing and signal int... » read more

Applications And Low Power
By Ed Sperling - 12 May, 2011 - Comments: 0

By Pallab Chatterjee As new process technologies are being developed to make devices smaller, they are also driving the operating power lower for the devices and systems. The goal is to reduce the power requirements for the system and hence increase the functional life on a single battery charge. This concept has worked in the semiconductor industry from 10-micron processes down to the 6... » read more

The Impact Of Triple Play
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ann Steffora Mutschler Not so long ago there were multiple networks that supported different kinds of traffic—a telecommunications network based on high-reliability protocols, the Internet for burst-centric data traffic and video distribution networks. From the consumer standpoint that was highly inefficient. Managing three subscriptions from three service providers was unnecessary, w... » read more

Talk, Talk And More Talk
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ed Sperling To anyone who owns a cell phone—and there are at least several billion people who claim that distinction these days—it’s not surprising that bad reception lowers battery life. More bars, while not the most accurate gauge of a signal, are at least an indication that you can extend the time between charges even if you’re watching streaming video. But work is under way a... » read more

Top 5 Reasons For Power Delivery Failure
By Matt Elmore - 12 May, 2011 - Comments: 0

By Matt Elmore Technology scaling has brought with it a myriad of causes for power delivery network (PDN) failure. Even a few years ago, it was simply enough to run static and dynamic power analysis to expose any voltage drops caused by weak power routing. No one cared about modeling the package and PCB. To account for clock jitter, you could simply throw in a whole nanosecond of clock uncerta... » read more

Power Noise Analysis For Next Generation ICs
By Various Writers - 12 May, 2011 - Comments: 0

In advanced technology nodes, SoC designs face complex power supply challenges driven by changes such as higher gate placement density, smaller wire and via geometries, and lower supply voltages in sophisticated, multi-layered packages and boards. The challenges associated with power delivery networks (PDN) anywhere on the die, package and board designs can be seen in all types of ICs, includin... » read more

The Real Value Of An LP Methodology
By Luke Lang - 12 May, 2011 - Comments: 0

By Luke Lang “What are some of the low-power mistakes that you have seen?” That is, by far, the most popular question asked by designers. And it’s a very good question. Why re-invent the wheel? Why repeat mistakes? It’s a lot easier to learn from someone else’s mistakes than from your own. Clearly, every company is different, and every design is different. But there are lots of co... » read more

Intel’s New Machine
By Barry Pangrle - 12 May, 2011 - Comments: 0

By Barry Pangrle Power is one of those product characteristics that touches on every phase of the design and verification process all the way from the system architecture down to the fabrication process used for the actual IC implementation. In this month’s blog we take a look at process technology and in this case, it appears to be the case that the technology rich are getting richer. On... » read more

Managing The Path Of Least Resistance
By Ed Sperling - 12 May, 2011 - Comments: 0

One of the great lessons of physics is that the natural order of things is the path of least resistance. Liquid flows to the lowest spot unless restrained by some sort of dam. Electrons flow through the channel with the least resistance and the highest conductivity. There are a couple of twists in the low-power engineering space, however, that can be classified as supra-natural. One is that ... » read more

Experts At The Table: Power Budgeting
By Ed Sperling - 12 May, 2011 - Comments: 0

Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul van Besouw, presi... » read more

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