April 2013 - Page 3 of 6 - Semiconductor Engineering

3D Integration
By Katherine Derbyshire - 23 Apr, 2013 - Comments: 0

By Katherine Derbyshire It’s a central problem of integrated circuit scaling. While transistor delay goes down along with channel length, interconnect delay goes up. The 90 nm technology node featured a transistor delay of about 1.6 ps, while a 1 mm long interconnect wire added about 5x102 ps. For the 22 nm node, the ITRS estimates transistor delay at 0.4 ps, but interconnect delay at abou... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 19 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

Design-For-DSA Industry Begins To Assemble
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs. DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from th... » read more

Fixing DP Errors: Colors Or Rings
By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Foundry Models In Transition
By Jeff Chappell - 18 Apr, 2013 - Comments: 0

By Jeff Chappell There may have been a time when AMD founder Jerry Sanders famous quote: "real men (i.e., real companies) have their own fabs” rang true, but in today's business climate it seems quaint at best. Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues ... » read more

Waiting For 3D Metrology
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear. 3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die ... » read more

CMOS And SOI Invade RF Front End
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The next-generation 4G wireless standard known as long-term evolution (LTE) presents some new and difficult design choices for OEMs. One of the more difficult choices involves the less glamorous, but arguably the most critical part in a handset—the radio-frequency (RF) front-end. Typically, the RF front-end often comes in a module and includes various key components, such ... » read more

Experts At The Table: Issues In Metrology And Inspection
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing f... » read more

Upbeat Prediction
By SEMI - 18 Apr, 2013 - Comments: 0

By Clark Tseng The semiconductor industry started out quite strong in 2012 but declined rapidly in the second half of the year, resulting in a slight year-over-year decline of 2.7% in worldwide semiconductor sales. On the other hand, worldwide capital equipment market recorded a decline of 15% from $43.5 billion in 2011 to $36.9 billion in 2012 according to the SEMI WWSEMS report. While indust... » read more

Mask Data Preparation Flow For Advanced Technology Nodes
By Various Writers - 18 Apr, 2013 - Comments: 0

The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes. This trend increases at 20 nm and below. That predicts new challenges in mask data preparation flow for advanced technology nodes. We have developed a mask data preparation flow to tackle th... » read more

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