Waiting For 3D Metrology

While different parts of the semiconductor industry have embraced 3D transistors and die, there are still huge gaps on the tools side.


By Mark LaPedus
Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear.

3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many chipmakers are still developing these technologies and face several process control challenges.

“In our industry, a lot of segments are metrology-limited,” said Christopher Bencher, a member of the technical staff at Applied Materials. “Overlay metrology is the number one area where we are limited. There is also a challenge with 3D devices like finFETs and 3D NAND. You have to be able to characterize them in 3D.”

As with many fab tool markets, there is a disconnect between the rhetoric from chipmakers and equipment vendors. Process control tool vendors insist they are ready for the 3D era. In contrast, chipmakers say many of the existing metrology solutions are running out of steam.

For example, some 50% of the process steps in a fab are devoted to inspection and metrology alone. About 10% of those steps use the workhorse metrology tool in the fab—the critical-dimension scanning electron microscope (CD-SEM). With finFETs, the CD-SEM is being stretched to its limits. “Three quarters of the steps can be handled by a conventional CD-SEM,” said Eric Solecky, senior manufacturing engineer at IBM. “This percentage is growing. It’s that fraction for 3D information that we don’t have a solution today for an image-based tool.”

Near term, there are other challenges in process control. “The main gaps in general are next-generation defect inspection, next-generation charge particle imaging, and next-generation scatterometry profile metrology,” said Benjamin Bunday, senior technical staff member at Sematech. Longer term, the industry also lacks a process control solution for graphene, carbon nanotubes and directed self-assembly (DSA).

Metrology madness
Several tool types—AFM, CD-SEM and OCD—can handle most requirements for today’s planar chips. Atomic force microscopy (AFM) uses a tiny probe to enable measurements. The CD-SEM is used for top-down measurements. And used for CD and overlay, optical scatterometry (OCD) measures the changes in the intensity of light.

But the process control world changed in 2011, when Intel rolled out the industry’s first finFETs. Using a transmission electron microscope (TEM), Chipworks recently discovered that the traditional one-to-one ratio between structures and transistors doesn’t apply with Intel’s tri-gate technology. In fact, one transistor can have multiple fins—six or more—while one fin can have multiple transistors, according to Chipworks.

So for finFETs, a given metrology tool must measure and characterize the separate pieces in the structure, such as the gate, fin height, sidewall angle and others. Each of those parts also requires one or more separate measurements.

The question is which single metrology tool can handle all requirements for structures such as finFETs and 3D NAND? The answer: None of them. There is no silver bullet. “We are already in a deluge of data,” said Jason Osborne, senior systems design engineer at Bruker. “We’ve got many systems making multiple measurements on the same structures and not getting the entire answer off any one system.”

In one possible finFET metrology flow, the fin is measured by the CD-SEM or AFM, and then, the results are feed to the OCD tool. Another possible metrology flow involves the CD-SEM, OCD and a TEM. The TEM, a system that shoots a beam of electrons through a tiny specimen, is used to validate the OCD model. “What you are trying to do is make your scatterometry model more robust,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries.

Intel, meanwhile, uses a combination of undisclosed tool technologies within its finFET process control flow. “We need all solutions,” said Adam Schafer, area manager of metrology and inspection at Intel. “We need to combine them.”

In process control, the biggest challenges for Intel can be summarized in three words—cost, noise and throughput. “Noise is one of our top problems. And it is really distinguishing the signal from the noise in any one of our techniques,” Schafer said.

Each tool type has its own set of issues. “If you are talking about CD-SEM, my CD measurement is traditionally top down. That’s not enough. I cannot control my processes with those CDs,” said Alok Vaid, senior member of the technical staff at GlobalFoundries. “Regarding OCD, it’s a solution, but it’s too complicated. So if you look at 14nm, 10nm and beyond, I don’t think the small dimensions are an issue for OCD. In fact, it can work in your favor. The problem is correlations.”

For AFM, the challenge is to measure finFETs in 10nm to 20nm spaces and characterize the profiles and shapes, he said. “We can’t leave optical tools such as ellipsometry out of the picture. Since everything is going 3D, now you want to measure those thicknesses and compositions on actual 3D structures,” he said.

The solutions
For some time, GlobalFoundries and others have been talking about the solution to the 3D problem—hybrid metrology. In this approach, separate tool technologies are used in a flow. The challenge is to put rival tool vendors in the same flow and tell the competitors to collaborate and share proprietary data with each other. “Let’s take an example. You have a CD-SEM supplier. You have an OCD supplier. And let’s say you want to overlap them and get my results. You can’t do that unless you get those guys to draw an algorithm together and get them to collaborate,” Vaid said.

While hybrid metrology is perhaps the wave of the future, tool vendors are also improving their respective technologies. For example, using Applied Materials’ CD-SEM, IBM conducted measurements in a theoretical gate-all-around finFET with silicon nanowires. In this experiment, “you see nice defined edges, even when you are beyond the resolution image,” said Ofer Adan, managing technology and marketing manager at Applied Materials. “So can we go beyond 14nm? What this work tells me is that a CD-SEM can go down to 6nm on a gate-all-around device.”

This is not to say the CD-SEM can handle all finFET requirements. “It cannot see whether or not there is an undercut. We need to work together with the OCD guys,” Adan said.

Overlay is another challenge and OCD is being stretched to the limits. KLA-Tencor recently unveiled a dimensional metrology system, which includes a new OCD technology based on a laser-driven source. “We think this is an inflection point for scatterometry,” said Andrei Shchegrov, director of advanced development at KLA-Tencor. “Our signal-to-noise gets a huge boost across a very wide range of wavelengths. We found the increased sensitivity due to the light source allows us to see things we couldn’t see before. It allows us to measure deep structures like high-aspect ratio 3D NAND flash.”

Despite the breakthroughs, the industry is still searching for new and better 3D metrology solutions. There are some promising candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging. And X-ray scattering (CD-SAXS) could succeed OCD.

“The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said IBM’s Solecky. “So the question is, ‘Do you need 3D information on the smallest features?’ The answer is yes. Potentially, helium ion is the solution.”

Helium ion enables 3D images, but the technology also can damage a device. The industry is looking for ways to tweak the helium ion microscope, which would make it somewhat comparable to the CD-SEM. “Technically, this involves a lot of challenges to make (helium ion into) a CD-SEM kind of tool. Those are not unsolvable problems, but it requires a lot of investments,” said Bipin Singh, product manager for Zeiss, a supplier of helium ion scopes and other fab tools.

As a replacement for OCD, the industry is looking at CD-SAXS, an X-ray scattering technology based on a synchrotron radiation source. “If you want 3D structures, you can certainly do it with CD-SAXS,” said Joseph Kline, a materials engineer at NIST. “The main limiter for CD-SAXS is throughput. Most of the measurements with CD-SAXS are done with a synchrotron source. Clearly, we are not going to have something like this in the fab. We are trying to figure out how to get a new source and make it work.”

There are other major gaps in metrology. For example, the current buzz in lithography centers on DSA, but it’s unclear if the industry has a metrology solution. “Metrology needed for DSA is really not different than the metrology needed for the rest of the industry,” said Applied’s Bencher. “You need to measure the registration of the holes. Now, when you are defining all of your holes by a mask, things tend to shift systematically, at least within the mobile region of the wafer. So how do you obtain an overlay measurement when things on the local level are shifted randomly? That’s not clear. It requires a different way of thinking.”