August 2013 - Page 3 of 9 - Semiconductor Engineering

Making Time to Do It Right
By Jon McDonald - 22 Aug, 2013 - Comments: 0

By Jon McDonald Change can be a very difficult thing. Most organizations I talk to about adopting system-level design know it’s a worthwhile investment. They believe it will have a positive return. They genuinely want to improve their processes, but believe they don’t have time to invest in making the change. In a recent conversation I heard an excellent encapsulation of this thinking. It ... » read more

DDR White Paper
By Various Writers - 22 Aug, 2013 - Comments: 0

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

Case Study: Microsemi Memory Interface
By Various Writers - 22 Aug, 2013 - Comments: 0

Microsemi qualified a structured approach to mixed-signal SoC verification using Questa ADMS, systematic pre-planning, and the OVM. To view this white paper, click here. » read more

Managing Memory With Embedded Software
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler Memory is shaping up to be a key leverage point for embedded software going forward as it represents such a large fraction of the silicon real estate in today’s SoCs. Managing memory effectively and memory bandwidth also represents a significant fraction of the potential bottlenecks and the power dissipation. As such, everything embedded software can do to enhance h... » read more

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Stacking The Deck
By Javier DeLaCruz - 22 Aug, 2013 - Comments: 0

By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

DDR White Paper
By Various Writers - 22 Aug, 2013 - Comments: 0

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

Completing System Design Flows With Emulation
By Frank Schirrmeister - 21 Aug, 2013 - Comments: 0

By Frank Schirrmeister Earlier this week, I participated with Mike Gianfagna (Atrenta) and our own Jason Andrews in a webinar hosted by Gary Smith called, “ESL - Are You Ready?” One of the very interesting discussion topics was how hardware-assisted verification has become the missing element in complementing different execution engines to enable software development and verification in de... » read more

Blog Review: Aug. 21
By Ed Sperling - 21 Aug, 2013 - Comments: 0

By Ed Sperling Mentor’s Michael Ford recalls the worst meetings in the world—ones that involve materials in the manufacturing process. Unfortunately there were a lot of them, so they were more like working in a recurring nightmare. Paging Freddie Krueger. Synopsys’ Karen Bartleson talks with Angisys CEO Anupam Bakshi about why EDA companies need to collaborate, and what’s the risk ... » read more

System Bits: August 20
By Ann Mutschler - 20 Aug, 2013 - Comments: 0

RF jammer technology To thwart electronic warfare technology, a research team at the Georgia Tech Research Institute (GTRI) is developing a new generation of advanced radio frequency (RF) jammer technology as part of a project known as Angry Kitten by using commercial electronics, custom hardware development, novel machine-learning software and a unique test bed to evaluate unprecedented level... » read more

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