February 2015

The Week In Review: Manufacturing

At the SPIE Advanced Lithography conference in San Jose, Calif., there were several takeaways. First, the battle for lithography share is heating up at Intel. “We believe Nikon still holds a decent position at Intel, but with ASML gaining some share at 10nm. Nikon could regain some share with its new platform at 7nm, in our view, but it is early to tell. We believe Nikon has improved its posi... » read more

The Week In Review: Design/IoT

Mergers & Acquisitions NXP acquired Quintic’s Bluetooth Low Energy and Wearable businesses, adding BLTE to their low power RF-connectivity portfolio. The team of approximately 65 is expected to join NXP when the deal closes in Q1 2015. Tools Cadence unveiled the integration of Forte's Cynthesizer with their own C-to-Silicon Compiler. The result is the Stratus high-level synthesis... » read more

Extra! Extra! Read All About It!

ASML announced that they are going into the pellicle business at 2:15pm on February 25 at the SPIE Advanced Lithography Symposium in San Jose. These are not your garden variety plastic membrane pellicles, mind you, but rather EUV pellicles made out of 50nm thick polysilicon film and stretched on frames that can be attached, removed and reattached on EUV masks. Dr. Carmen Zoldesi of ASML reveal... » read more

Mentor Graphics Buys Tanner EDA

By Ed Sperling & Brian Bailey [getentity id="22017" e_name="Mentor Graphics"] has just purchased [getentity id="22561" e_name="Tanner EDA"] for an undisclosed sum, according to sources close to the deal. The acquisition moves Mentor squarely into the analog and mixed signal tools world, while positioning it to play a much bigger role in the Internet of Things market. Mentor isn't t... » read more

Obsolescence Isn’t Always Good

One of the main reasons smartphones are pervasive around the globe is that their cost is subsidized. They can be replaced every couple of years with minimal pain as designs get slicker, more energy-efficient, and new features are added such as better screens or better performance. That works particularly well when a consumer's out-of-pocket expenses after trading in an older model are basically... » read more

Partition Lines Growing Fuzzy

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

Incremental Design Methodologies

There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

IP Market Booms At Advanced Nodes

As [getkc id="81" kc_name="SoC"] design and manufacturing costs rise, system OEMs are wringing as much of that increase as they can from ASIC vendors. The result is that engineering teams on the design and test side are being constrained by budgets at a time when complexity is rising and time-to-market pressures are increasing. At least one segment is benefiting from directly this. Budgetary... » read more

Custom Versus Platform Design

The increase in [getkc id="81" kc_name="SoC"] complexity is being mirrored by a rise in complexity within the markets that drive demand for those chips. The upshot is that a push toward greater connectivity, lower power and better performance—and all for a minimal cost—has turned the pros and cons for custom design vs. platforms and superchips into a murky decision-making process. For t... » read more

First Time Success And Cost Control

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

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