28, 20nm Nodes Demand Advanced Power Management

By Ann Steffora Mutschler
With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible.

Sub-Clock Power Gating
Far from a new technique, power gating essentially stops all the current flowing into the system because when the electronic device is not being used, it helps to reduce the ideal mode power or the leakage current. “Essentially we turn off the switch so that there is a break or discontinuity in the whole circuit. We usually do that in an ideal mode because in the operational mode we want the devices to be working,” explained Aveek Sarkar, vice president of product engineering and customer support at Apache Design.

“Then, when it comes to sub-clock power gating, within a clock period, let’s say you are running a 100 MHz clock, it’s a 10 nanosecond clock period. But within that 10 nanoseconds we are actually doing logic operations during all of that period because devices tend to be so much faster nowadays. Most of the operation may end up finishing within one nanosecond or so. The remaining nine nanoseconds you pretty much have a dead period before the next set of activity comes along. Can we shut off the power coming into the device for that nine nanoseconds? If you do that and do it efficiently we can even get 25X power efficiency,” he continued.

Clock Power Gate Structures
Clive Bittlestone, a Texas Instruments fellow, noted during a panel session at the Design Automation Conference last month that in advanced power management, clock power gate structures are useful.

Adaptive Body Biasing
Adaptive body biasing is a technique that is, “becoming pretty interesting especially if you look at FD-SOI (fully depleted silicon-on-insulator),” Sarkar noted. Last month, STMicroelectronics announced it would use GlobalFoundries as an additional source for its 28nm and 20nm FD-SOI process.

He pointed to the comment by Philippe Magarshack, ST’s group vice president for technology R&D, in which he said this can be used either for the high-performance mode or the low-leakage-current mode by biasing the substrate dynamically, meaning that some parts of the design can be running at a high frequency mode and simultaneously part of the design can be working in the low leakage mode. “That’s definitely one of the directions we see. Obviously it introduces a lot of additional complexity.”

On-Chip Regulators
Yet another technique is the use of on-chip regulators. With advanced power management, one of the common techniques used is near-threshold computing, which is to reduce the supply voltage that is significantly close to the threshold voltage but also means that the noise margin goes down significantly.

“Let’s say what threshold essentially means is that if you reach 300 millivolts, the device starts to operate in another logic state, but if your supply voltage is only 400 millivolts then any small amount of derivation can cause a device to change state. When we had the supply voltage at 1 volt, we had a large amount of noise margin—400 or 500 millivolts—that definitely does not exist, so we have to be more careful about modeling and predicting noise in the circuit and make sure that the noise that’s being generated does not have a harmful effect on the end device especially because the noise margins are so much more compressed,” Sarkar explained.

The primary reason to go to these low supply voltages is to reduce power. “If you look at a supply voltage of 1 volt versus 700 millivolts—just because you go to 700 millivolts do you reduce your power consumption by half because it’s V2 and you automatically reduce it by half? In order to enable this type of near-threshold computing architecture you need to use more complex power supply devices; the board level regulator does not suffice. Dadi Perlmutter from Intel talked about this in his ISSCC keynote. Because we cannot manage the noise on the board and the package that carefully they are moving to using on-chip voltage regulators—they can reduce the supply voltage significantly. The other benefit with on-chip regulators is that dynamic voltage scaling is much more possible,” he said.

However, there are issues with using on-chip regulators because unlike off-chip regulators they have limited capabilities: if current is drawn too fast, it may not be able to respond and supply the voltage quickly. To account for this, some tools allow for the creation of models of this on-chip regulator and use this for dynamic voltage drop analysis to predict what the behavior of the circuit is going to be in a real-world scenario.

At the end of the day, the biggest bang for the buck is always making architecture changes high up in the level of abstraction, said Nikhil Sharma, vice president of engineering at Calypto. “That’s there no matter what the geometry is. Based on the actual gate level and transistor level tricks you can get some power savings but our hope is that we can convince people to make changes and use power technologies to help facilitate or automate some of tough decisions that they need to make at hopefully the architectural level or the RTL.”