3 Ways To Reload Moore’s Law

A lateral shrink of transistors cannot continue indefinitely. There aren’t enough atoms.


The electronics revolution has been enabled because the cost and power per transistor has decreased 30% per year for the last 30 years — a fact usually associated with Moore’s Law. This has been accomplished by simply reducing the transistor size while offsetting increased costs of equipment and mask levels, and by increased productivity from improved yield, throughput and wafer size.

This lateral shrink of the transistor cannot continue indefinitely, though, because we are running out of atoms. For example, the fin in a finFET is about 60 to 80 atoms across. Soon, the only way for even a slower version of to continue will be to create 3D devices by adding device layers with a less than proportional increase in cost and power.

But there are three developments could enable a reload of Moore’s Law:

  1. Self-assembly of devices vertically to scale cost per transistor;
  2. Replacing dynamic RAM with static RAM to eliminate non-computation power drain, and
  3. Use massively multi-core processors to scale power per transistor.

Feasibility of these developments are at the center of many recent discussions involving next-generation electronics.

Self-assembly is being developed in incremental steps. Self-assembled 3D memory cells are very close to production in the form of . In 3D NAND, a vertical chain of 20 to 30 self-assembled memory cells are created in a single lithography step, with the control logic fabricated in the silicon substrate first. A vertical memory chain of 128 bits is on the horizon, which translates to 14 more years for a conventional Moore’s Law roadmap. Replacing DRAM with ReRAM, as discussed below, would enable vertical stacked memory in microprocessors.

From a recent Micron/Intel announcement on 3D NAND.

The same strategy can be envisioned in microprocessor logic sections by including vertically oriented simple logic strings.

The next step to move Moore’s Law along would be to create multiple layers of control logic and vertical memory/logic chains. The brute-force solution to multilayer devices is to package stacks of multiple backside-thinned devices, which is routine in very thin form factor flash memory. The introduction of through-silicon vias is a next step, which reduces packaging cost but does not really give multi-generation Moore’s Law leverage. IBM has described a multilayer microprocessor “brick.” Again, this should give performance leverage, but no cost, and power scaling.

Self-assembly is the only way to create cost-scalable multiple layers of programmable control logic. The good news that there is 15 years to work it out, and several building blocks are already in place. Directed self-assembly (DSA) is in pre-production in advanced multi-exposure patterning. DSA uses a block copolymer consisting of two different organic polymers connected in a single molecule. Making an electrically functional block polymer, with one half being a conductor or semiconductor, is a subject of active research, and suggests that regular arrays of devices may be possible. The semiconductor material is critical. Current research in carbon nanotubes and graphene suggests a possible path. It would seem possible to create regular arrays of standard cells and then custom-wire them together, or make the logic programmable.

Another self-assembly strategy is “biomimetic,” in which biological binding mechanisms are used to place prefabricated objects at specific locations. Attaching nanowires and peptide nanotubes to a surface has been demonstrated using protein antibody binding, so why not a carbon nanotube? An alternative is the use of DNA as both a functional electrical material that can be placed by binding to other DNA strands. This is an intriguing approach that obviously suggests the best know example of self-assembled logic — the brain.

Power scaling also can have an incremental solution. According to Rami Melhem, a computer science professor at the University of Pittsburgh, the largest power draw today is keeping DRAM updated.

Warren Jackson, a research at HP labs, agrees. He has identified using “crossbar memories based on ReRAM as a DRAM replacement” as a key objective of “The Machine” project at HP. The Machine is Hewlett-Packard’s vision for a new computer architecture that was announced last year. Moving microprocessors from DRAM memory to static ReRAM created in a separate set of layers, similar to 3D NAND, on top of the logic would enable Moore’s law growth in both cost and power.

“A cell phone battery would last 7 times longer if DRAM could be replaced,” Jackson observed. An 8x improvement translates to 6 years of Moore’s law growth.

HP is not alone in working on ReRAM, either. Crossbar recently announced commercial crossbar flash memory, and IBM researcher Geoff Burr reported on IBM’s work on vertically stacked ReRAM flash memory.

Once the power drain from dynamic memory has been eliminated, then the focus can move to the energy penalty of doing the calculations themselves. Pittsburgh’s Melhem pointed out that the power drain scales as somewhere between the square and cube of the clock frequency. Distributing a calculation over multiple processors working at a lower clock speed has an obvious power benefit. His group has created an analytical model that shows the energy savings can scale as high as the square of the number of processors. Melhem also was clear that “the advantage would scale to very large numbers of processors provided that the calculation could be broken down into parallel tasks.”

How might an ultra-multi- processor perform? The brain is a 10^9 times faster processor than the iPad, and comparable to the latest Fujitsu supercomputer, according to an article in Scientific American. The big difference is that the brain uses 20 watts of power, or 10 to the minus 7 times the power of the Fujitsu supercomputer. The neuron speed of the brain is only 100Hz, and the brain achieves its low power computation heroics by slow, ultra-massively parallel processing.

Reducing power consumption by reducing clock speed and using large numbers of cores to increase parallel processing is probably going to be part of a long-term Moore’s Law reboot. The current trend to multicore and multi-processor systems certainly shows the way forward. The economic engine of electronics is not simply going to stop, and self-assembly combined with parallel processing offers a scalable path to reload Moore’s Law.


DChapmanTezzaron says:

Great article, but it is ironic that Mr Watts would miss a key point about power. With reference to 3D products he says “Again, this should give performance leverage, but no cost, and power scaling.”, and that actually is not accurate. 3D, done properly, produces tremendous power savings. The principle is simple. Shorter distance means lower parasitics (capacitance and inductance). On ICs power is lost to leakage and switching. But switching itself is not the power hog…most of the power goes to switching the load…most of which is parasitic. Most 3D efforts have been focused on 3D packaging and I agree, in that context, only small improvements are available. But Tezzaron is working on dis-integrating circuits. We spread them vertically across multiple die rather than horizontally across a single die, which dramatically reduces signal distance and so dramatically reduces power. We send signals microns rather millimeters. And make no mistake, this also reduces cost. Anyone who can do more with less saves money. Since power has become the primary limiter on integration, disintegrated architectures allow much higher performance with existing technology…and that is far more cost efficient than exotic new materials and the manufacturing facilities to use them.

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