3DIO IP For Multi-Die Integration

By Lakshmi Jain and Wei-Yu Ma

The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity presents two significant challenges: manufacturability and cost. From a manufacturing standpoint, these processing engines are nearing the maximum size that lithography machines can etch on a reticle. As die sizes increase and yields decrease, the cost per die can rise substantially.

Gordon Moore once said, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” To meet the demands for higher performance, the chip design industry is shifting from system-on-chip (SoC) to system-in-package (SiP) through wafer-level packaging.

Fig. 1: Multi-die heterogeneous systems.

A heterogeneous SoC entails partitioning the SoC at the IO or core level, using a modular approach with different building blocks. This offers several advantages, including supporting SoCs that are growing beyond reticle size, improving die yield, and enabling design modularity. However, a heterogeneous die introduces new challenges which include increased design complexity due to close interaction between the dies and package, supporting testability across assembly and manufacturing processes, and thermal management due to the proximity of the dies. 3D integration enables heterogeneous integration of IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems that have high performance, low cost, and compact size requirements.

Advances in packaging enable multi-die systems

Emerging semiconductor applications that require the processing of massive quantities of data are driving the progress of advanced packaging. Various advanced packaging technologies, side-by-side or vertical placement, have emerged as part of the implementation of heterogeneous integration technology. 2.5D and 3D packaging have gained popularity as prominent solutions, each offering unique advantages and challenges, making them essential considerations for semiconductor manufacturers and designers.

In 2.5D packaging, two or more chips are laid side by side with an interposer connecting one die to another. The interposer acts as a bridge, connecting the individual dies and providing a high-speed communication interface, allowing greater flexibility in combining different functionalities on a single package. By stacking dies on an interposer, 2.5D packaging reduces the overall footprint of the package (compared to 2D), making it ideal for smaller and thinner devices. Interposers and bridges provide a large number of high-density BUMPs and traces, which helps in increasing bandwidth.

In 3D IC technology, chip connections are made through vertical stacking, enhancing the overall performance and functionality of the package. This allows the integration of chiplets with multiple layers and functionalities. A key trend of this integration – especially for 3D packaging technologies such as hybrid bonding – has led to an aggressive shrinking of the BUMP pitches between the chiplets and the resulting reduction of the corresponding interconnect distances and related parasitics.

Scalability: Interconnects

Driven by the demands for greater bandwidth and advances in manufacturing processes and packaging technologies, there has been a significant change in interconnects from traditional copper uBUMP to the most advanced uBUMP using 40um pitch, scaling even further down to 10um (figure 2).

Fig. 2: Scaling of BUMP pitches (Source: status-of-the-advanced-packaging-2023, Yole Intelligence, June 2023)

In the 2.5D scenario, the connection between chips is made through Redistribution Layers (RDL) on an interposer, with the distance between chips usually in the order of 100um. As chip stacking technology advances in the 3D scenario, the use of uBUMP for vertical stacking of chips allows for direct connection between two chips, reducing the distance to less than 40um. This significantly reduces the size of the substrate. In addition, in 3D integration, the IO signals for transmission no longer need to be placed at the edge of the chip. Furthermore, by using the hybrid bond technology in a system of integrated chips (SoIC, 3D), the vertical connection between chips is even tighter. Hybrid bonding connects dies in packages using tiny copper-to-copper connections (<10um). The smaller BUMP pitch of a hybrid bond allows for thousands of IO channels in the same area, further increasing integration and performance. This advancement significantly improves data bandwidth even at lower operating frequencies (compared to 2.5D). Therefore, given this technological progress, opting for a solution based on simple digital IO such as Synopsys 3DIO (figure 3) not only enhances the reliability of IO circuits but also shows better quality of results in terms of area efficiency versus Serial IO.

Fig. 3: 3DIO area efficiency.

3DIO IP solution offers flexibility, scalability with optimal performance

Synopsys 3DIO IP Solution (figure 4) is specially tuned for multi-die heterogeneous integration with a versatile offering, enabling the optimal balance of power, performance and area (PPA) in 3D stacking for emerging packaging demands. Furthermore, the 3DIO IP enables faster timing closure, which is a critical challenge in die-to-die integration.

Fig. 4: Synopsys 3DIO IP Solution is architected to support 2.5D, 3D and SoIC packages.

Synopsys 3DIO IP Solution offering comprises the following:

• Synopsys Synthesizable 3DIO includes a synthesizable Tx/Rx cell compatible with Synopsys standard cell libraries and a configurable charge device model (CDM) for optimal ESD protection. As the number of IO channels are drastically increasing, the optimized Synopsys 3DIO solution leverages the automatic place and route (APR) environment to place and route the IOs directly on the BUMP. The solution supports both 2.5D and 3D packaging using micro-BUMP and hybrid BUMP. The Synopsys 3DIO cell supports a high data rate and offers the lowest power solution, with an optimal area that fits within the hybrid BUMP area.
• Synopsys Source Synchronous 3DIO (SS3DIO) extends the synthesizable 3DIO cell solution with a clock forwarding functionality to aid in lower bit error rate (BER) and ease timing closure between dies. The SS3DIO offers scalability to create custom-sized macros with optimal PPA and ESD. The TX, RX, and clock circuits support matched data and clock path, with data launched at the transmitting clock edge and captured at the corresponding receiving clock edge.
• Synopsys Source Synchronous 3DIO PHY is a 64-bit hardened PHY module with inbuilt redundancy, optimized for highest performance. The 3DIO PHY with CLK forwarding reduces BER and eases implementation along with optimal placement of POWER/CLK/GND BUMP (figure 5).

Fig. 5: Synopsys Synchronous 3DIO PHY view. (Source: Synchronous 3DIO PHY cross sectional view)

Summary

With the advancements in packaging technologies and increased density of interconnects, there is a significant rise in the IO channels for a given die area. The corresponding decrease in IO channel length increases performance but gives rise to the need for a more streamlined interface. Synopsys 3DIO IP Solution offers versatile solutions for customers to implement tunable, integrated multi-die design structures. The optimal area of the Synopsys 3DIO IP Solution offering is carefully designed to be within the BUMP, providing significant advantages in implementation and signal routing. In 3D stacking technologies, a source synchronous clock design for signal transmission can help customers achieve a lower BER and ease timing closure. Synopsys 3DIO IP Solution is tailored for multi-die integration, enabling customers to create efficient chip designs with faster time to market, accelerated with Synopsys 3DIC Compiler to ease integration and provide optimized PPA for a given technology. In addition to the 3DIO, Synopsys Multi-Die Solution includes UCIe IP and HBM3 IP.

Wei-Yu Ma is principal technical product manager for IO Libraries at Synopsys.