450mm And Other Emergency Measures

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months.

Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approaches ever materializes is questionable. The cost of developing 450mm or panel-level equipment is enormous, and there has to be enough industry support to provide a reasonable return on investment for enough companies with enough volume. Given the splintering of end markets and consolidation among big chipmakers, this may prove to be more of a rallying cry than reality.

In several presentations at SEMI’s Strategic Materials Conference this week, speakers plotted the technical possibility of extending Moore’s Law against the financial impact of continuing Moore’s Law. The bottom line is that no matter what steps are taken, the price per transistor will increase. As Ben Eynon, senior director for engineering development at Samsung pointed out, even if EUV lithography does become a commercial success, it has a wavelength of 13.5nm. “If we don’t get EUV in quickly, it will go to sub-wavelength right away.

Double patterning with EUV isn’t a one-to-one replacement with 193nm immersion, though. Double patterning with immersion is faster than with EUV, which means the price for double patterning with EUV may be higher than quadruple or octuple patterning with immersion. Shooting a drop of molten tin with a high-powered laser also splatters the tin across a very expensive mirror, requiring the mirror to be replaced. And given that 193nm equipment is already fully depreciated, EUV is likely to become a complementary technology to immersion rather than a full replacement.

So where else can the economies of scale associated with node shrinks come from? The answer isn’t clear. One possibility is nowhere, providing there is enough of a performance boost and power reduction to make it worthwhile. Srinivasa Banna, fellow and director of advanced device architecture at GlobalFoundries, said that with new transistor structures there will still be a 10% to 15% performance improvement and a 35% decrease in power. That may be enough to warrant higher prices for chips.

Banna noted that more self-aligned features, lower-resistivity interconnects and low-permittivity dielectrics, as well as new device architectures, will be key enablers for continuing Moore’s Law. “We need to optimize resistance,” he said. “That is the innovation of the next 10 years.”

On the process side, Adrien LaVoie, director of engineering at Lam Research, pointed to atomic-layer deposition, etch and clean as three essential technologies for future nodes. But as with EUV versus immersion, he said ALE and ALD will never catch up with the speed of pulsed laser deposition. Still, he said that ALE will have a long future, migrating from the transistor to the back end.

So what does all of this mean for the future of scaling? There are three takeaways.

First, continued scaling is technically possible and likely to happen for the foreseeable future. The big challenge isn’t about technology, though. It’s about cost. If costs can be brought under control, then scaling will continue for at least the next decade. If they can’t, it may continue for some time, anyway, if power/performance improvements can be maintained.

Second, end markets are in such flux that it’s unclear whether there will be enough volume to drive massive investments beyond what is already in the works. That still could be 5nm or 3nm, and with time between nodes extending to as much as four years, that could add another decade or more for scaling. The challenge here isn’t just on the equipment and foundry side. It’s across the semiconductor ecosystem. It’s much more expensive to develop analog IP, for example, at 5nm, which means it will become increasingly more difficult to find. That could drive up chip costs or make power/performance gains less optimal.

Third, new computing architectures such as neural networking and quantum computing could well replace the Von Neumann architecture in a number of markets. Those approaches put less emphasis on process and more emphasis on architecture. Even advanced packaging, such as 2.5D, 2.1D and fan-outs, which still rely on Von Neumann approaches, may provide advantages such as flexibility and throughput that are becoming increasingly difficult to achieve with process alone.

So how much is device scaling really worth? That appears to be the big question no one is directly asking. At this point, there doesn’t seem to be a good answer.

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