A Node Too Far?

Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more problems pop up in other places.

At each new node parasitics are becoming more challenge. In effect, what used to be problems that were handled at the back end of the design-to-manufacturing flow are now moving to the front end. Shift left now applies to more than just verification and debug. It now applies to everything, from the overall multi-component system that needs to be simulated up front to the impact of circuit aging on signal integrity.

While 5nm and 3nm are likely to happen from a manufacturing standpoint — there are even plans to add CFETs and CNFETs at 2nm and 1nm, respectively — the bigger issue may be how long and how well those chips function reliably, and for how long. At a time when the EDA tools and the manufacturing equipment have reached an apex in terms of technology, problems like electron tunneling, age-related signal drift and electromagnetic interference are becoming first-order issues.

This has been a topic of discussion on the design side for some time. It’s well understood that analog circuits don’t benefit from shrinking, particularly into the single-digit nanometer realm. But below 7nm, digital circuitry begins to behave like analog circuitry — with an increasing number of quantum effects thrown in.

There simply is not enough insulation to prevent noise from disrupting signals. That affects where certain critical circuits can be placed on a die, and it impacts decisions about how far to move certain data to limit possible disruptions. This may not have been the initial goal of near-memory or in-memory computing, but it is likely to be one of the drivers over the next couple nodes.

Noise comes in many flavors. There is noise from power, heat, electromagnetic interference, substrates and switch, and there is noise from the environment when advanced chips are used in automotive or cloud AI applications. All of them are relevant at 5nm and below, and with each new node the dielectrics become thinner and the sensitivity of thinner devices increases.

Or, looked at from a different angle, tolerances tighten across the entire design and there is less margin to deal with it. Margin is now budgeted at a system level, and that system extends well beyond a chip because it affects the overall functionality of a much larger system or system of systems. But even where margin is available on a larger system level, it may impact the performance at the nano level.

Below 5nm, quantum effects become increasingly problematic, as well. Fabs have been dealing with quantum effects for years. When something is printed on a die, it shift for reasons that no one can explain. For the most part, the IC design world has been insulated from these effects through restrictive design rules imposed by the foundries, but at 5nm and below, these effects need to be considered up front in the design because a 1nm shift that was inconsequential at 40nm can cause significant problems at 3nm. That makes it harder to design to tight specs until these effects are better understood and included in EDA tools, and so far that hasn’t been a top priority for the industry.

Taken as a whole, this does not slow progress in chipmaking, but it does fundamentally change it. Chips still will get faster and use less power than in the past, but not everything will be packed onto a single die. Every major foundry and packaging house has recognized this shift is coming, and they have been developing a slew of multi-die packaging options. Some of those developments have been proven in the market in volume. And even the most stalwart proponents of continual shrinks has come around to recognizing that not everything needs to be developed at the same node.

So whether planar SoCs are still mass produced at 3nm or 2nm, or whether they are increasingly multi-die implementations that include 3nm and 2nm logic isn’t clear. But physics definitely is catching up to planar scaling, and at some point in the next few nodes the market will recognize that the next node is a node too far — at least for everything that is now being packed onto a single die.