A new technical paper titled “PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation” was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology.
Abstract
“3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design flow of 3D ICs, the placement stage includes a differentiated design step to assign instances to different tiers, i.e., top or bottom, called tier partitioning. Despite its importance to overall circuit performance, previous tier partitioning approaches have not taken power-performance-area (PPA) optimization into account, leading to degradation in timing and increased power consumption. In this paper, we propose a novel tier partitioning method in 3D IC placement that concurrently optimizes all PPA-relevant aspects, i.e., intertier cuts, overlapping areas, tier transitions along timing-critical paths, and local/global area balance. We first reduce the problem complexity with netlist clustering based on logical and physical relations, and then formulate an integer-linear programming (ILP) model for each cluster to find an optimal solution. Experiments on various benchmarks demonstrate that our method achieves significant improvements over previous tier partitioning results in terms of all PPA metrics, including 1.23% reduction in power consumption, 24.08% reduction in total negative slack (TNS), and 3.44% reduction in wirelength on average.”
Find the technical paper here. March 2025.
Eunsol Jeong, Taewhan Kim, and Heechun Park. 2025. PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. In Proceedings of the 30th Asia and South Pacific Design Automation Conference (ASPDAC ’25). Association for Computing Machinery, New York, NY, USA, 879–885. https://doi.org/10.1145/3658617.3697733.
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