A Survey Of Our Low Power Blogs In 2014

Over the past year, we have written a number of blogs on low power IC design. Here at the end of 2014 approaches, let’s look back at what we have discussed
Our blogs covered methods to estimate and reduce power consumption in digital ICs. Our recommendation is that you do this early in the design cycle, such as the RTL coding stage, when you can have the most positive impact.

In the first part of 2014, the primary focus was on low power optimization at the RTL stage. We had several articles discussing both optimization techniques and the challenges to doing optimization at the RTL.

• In December 2013, Abhishek Ranjan blogged about the motivations for designing electronic systems with low power. He also gave a high-level overview of different power optimization techniques.
• January’s blog covered verification challenges and techniques for power-optimized designs, and it also identified recommended verification flows. Rob Eccles talked about the ways applying clock gating to reduce power can impact the verification process. The solution to this problem was described.
• In February’s blog, Qazi Ahmed described the importance of maximizing power savings and the impracticality of hand-optimizing designs for power. In an RTL design, there can be hundreds of possible optimizations. The challenges are to choose the best option, implement the required changes correctly, and then verify them.
• In April, Rob Eccles described some of the subtle issues that can lower the quality of power optimization. Low power design engineers will want to check for these issues.
• In our July blogs, Anand Iyer authored a two-part series providing a broad survey of power saving techniques. (See Part One and Part Two)
• Power optimization techniques were covered in more detail by Rob Eccles in our August blog. It focused on how to lower power consumption before RTL and at the RTL stage. Fine and coarse grain techniques were discussed.

In the second half of 2014, the focus shifted to RTL power estimation, including techniques and best practices. Power estimation is becoming an important element of RTL design, as designers try to decide on how to meet strict power requirements for their designs

• The reasons why power estimation should be done at the RTL are detailed by Anand Iyer in our September blog.
• The October blog covered RTL power estimation techniques.  It is often surprising that it is possible to get a reasonably accurate estimate of power consumption at the RTL stage. Techniques for achieving this are explained by Rob Eccles.
• In November, Rob Eccles examined memory-gating techniques. For many designs, memories consume most of the power. If there are memories embedded in your design, it will be important to look at memory gating.

Thanks for following our blogs over the past year. We hope they have been interesting and useful for you. Upcoming blogs will continue to expand upon these themes. Our goal is to share our expertise and experience in designing for low power with all designers so they can design better products.