Learn about a novel memory test system that can measure each cell’s switching current of STT-MRAM. The system was implemented in a gigabit class memory test system.
Authors: (Advantest) Ryo Tamura, Ibuki Mori Naoyoshi Watanabe; (Tohoku University) Hiroki Koike, Tetsuo Endoh.
A novel memory test system is needed for future STT-MRAM mass production that supports error bit analysis and its mode categorization on STT-MRAM chip measurement, as STTMRAM cell’s switching is a probabilistic phenomenon based on quantum mechanics. In order to meet this requirement, we successfully developed a novel current measurement module on gigabit class memory test system that can measure the time domain switching current of each bit with nanosecond and microampere resolution. Moreover, we demonstrated the world’s first results that our developed memory test system detects all error bits in fabricated STT-MRAM chip and categorizes error bit mode according to the switching characteristics of each error bit. This novel memory test system with the function of accurate and high speed time domain current measurement on the same level as single bit measurement equipment is expected to accelerate R&D and mass production of STT-MRAM and other applications such as ReRAM and PCM.
Click here to read more.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply