How machine learning-based root cause analysis can be used in achieving faster CDC analysis and RTL signoff.
Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of asynchronous clock and reset domains is growing heavily within these complex SoCs, leading to millions of clock domain crossing (CDC) violations at the SoC level. Each of these violations requires a dedicated review effort by the designers to ensure bug-free tape-out.
These millions of violations put a lot of strain on the chip project because of the need for a large number of engineers and their corresponding design expertise required to manage and achieve RTL signoff within the mandated time to market (TTM). Designers end up dealing with time- consuming iterative debug cycles in addition to spending a lot of time arriving at a potential root cause for every violation. All this manual effort causes a significant delay in overall debug cycle closure, CDC signoff, and TTM.
Synopsys’ next-generation industry-leading VC SpyGlass RTL signoff platform provides machine learning-based root cause analysis (ML-RCA) technology to provide a significant boost in designers’ debug productivity. This white paper discusses how machine learning-based root cause analysis can be leveraged in achieving 10X faster CDC analysis and RTL signoff.
Click here to read more.
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