New materials play a pivotal role, but solving integration problems remains a challenge.
Multi-die assemblies offer significant opportunities to boost performance and reduce power, but these complex packages also introduce a number of new challenges, including die-to-RDL misalignment, evolving warpage profiles, and CTE mismatch.
Heterogeneous integration — an umbrella term that covers many different applications and packaging requirements — holds the potential to combine components from several different processes into a single package. And it may be able to do so more cost-effectively and with better yield than integrating the same components on a single piece of silicon.
Placing devices in a single package also improves performance and reduces the circuit’s overall footprint relative to separate components on a conventional circuit board. But bringing those various components together on a single substrate is a major challenge.
Consider mobile devices, for example. These typically incorporate multiple sensors and transceivers alongside their memory and logic components. Analog and power components often need unique process steps not found in CMOS device manufacturing, as well as thicker metal and dielectric layers.
Most of the research on these issues has been on the leading edge of semiconductor design. But if the integration challenges can be solved, relatively small markets would benefit significantly, as well. One way to get there is to develop solutions that can work across different application domains, according to Tanja Braun, head of department and group manager for assembly and encapsulation at Fraunhofer IZM, during a presentation at the Materials Research Society’s Workshop on Materials Opportunities in Microelectronics Packaging and Heterogeneous Integration, which took place during the recent 2025 MRS Spring Meeting.
Fig. 1: Different packaging configurations, interposers and interconnect densities. Source: ASE
Interposers tie components together
Today, most heterogeneous assemblies utilize some form of interposer, which connects circuit components to one another and to the outside world. A single device might be placed on an interposer with fan-out wiring and integrated capacitors or other passive elements. Optical components might rely on waveguides embedded in the interposer. And several processing units might be connected by a bridge element with embedded wiring, as in Intel’s Embedded Multi-Die Interconnect Bridge (EMIB).
In all cases, the required interconnect and power density determine the choice of interposer material. But all of them face the same fundamental challenge — managing the coefficient of thermal expansion (CTE) difference between the silicon devices and copper-based system-level wiring. Fraunhofer’s Braun noted that when her team filled vias in an organic dielectric with copper pillars, the CTE mismatch resulted in shrinkage that caused cracks at the copper-dielectric interface. [1]
CTE management is especially difficult for power devices, which may generate substantial heat during operation. Power devices also require robust isolation to prevent arcing and reduce parasitic losses. Glass meets the isolation and thermal stability requirements, but it requires special handling.
Optical interconnects, which are of interest for intermediate-length connections in data centers, also pose unique challenges, according to Ning Li, associate professor at Penn State’s School of Electrical and Computer Science and Materials Research Institute. He noted that manufacturers would like to integrate waveguides and other passive optical elements into the interconnect package, but doing so requires careful control of the refractive index and refractive index contrast in the substrate.
Though power and optical devices pose special challenges, even interposers for general-purpose logic components need to be co-optimized with the rest of the design. For example, fan-out panel-level packaging is often proposed as a more efficient successor to fan-out wafer-level packaging. Panels allow parallel processing of more devices and, being rectangular, waste less space when tiled with rectangular devices. However, Braun said their dimensions place them in a gray area. Process and inspection tools that can meet the micron-scale dimensional requirements of redistribution layers for logic are mostly optimized for wafer-sized substrates. Even when tools that can handle large substrates are available, inspecting such small dimensions is inherently slow.
Keeping dies where they’re placed
Managing warpage and die shift is especially challenging for panel-level packaging. Chip-first, face-down fan-out processes place singulated dies face down on transfer tape on a carrier substrate. Glass carriers are often used to facilitate UV debonding. After the dies are encapsulated in molding compound, releasing the transfer tape separates the panel from the carrier substrate, exposing bond pads. Hybrid bonding takes place after aligning these pads to the interposer’s redistribution layer wiring.
The process is easier to describe than to accomplish. The transfer tape and the molding compound — both typically polymer-based — have different CTEs from each other and from the silicon dies and the carrier substrate. The transfer tape generally expands during the molding process, while the molding compound shrinks as it cools and solidifies. The complementary stresses can warp the panel, and they can pull individual dies out of their original locations, and therefore out of alignment with the redistribution layers.
Braun noted that warpage evolves over the course of the assembly process. The complete panel assembly, with heat sinks, stiffeners, and molding compound included, is likely to be less warped than the encapsulated dies alone. Accordingly, process optimizations should evaluate the overall result, rather than any specific process step.
Die shift, in contrast, tends to be “frozen” in place once the encapsulant has hardened. While a known, systematic shift can be accommodated in the RDL design, thermal anomalies, inhomogeneities in the molding compound, and similar factors can result in random shifts. Misalignment between the dies and the RDL wiring is especially difficult to detect in this kind of package because the hybrid copper-copper bonds connecting the two are hidden between the two layers.
Top-down visual inspection can readily detect deformed solder bumps and broken wire bonds but not interface contamination or misaligned hybrid bonds. Testing of both the individual dies and the package as a whole remains challenging.
Different approaches to deal with these issues are emerging. Gang Duan, Intel senior principal engineer and his colleagues, noted that his company’s EMIB package attempts to address die shift errors by designing pre-fabricated wells for die placement into the silicon “bridge” element.[2]
Another alternative, proposed by Braun’s group, depends on maskless lithography. After measuring the final positions of the dies, the fab modifies the RDL pad placements accordingly and fabricates a custom interposer with the updated locations. Whether this solution could meet the cost and throughput requirements of large-scale manufacturing is unclear. RDL fabrication is technically closer to CMOS interconnect processing than PCB fabrication, but the panel area is much larger than generally contemplated by wafer-focused design tools.
For power devices, workshop contributor F. Patrick McCluskey, professor of mechanical engineering at the University of Maryland, pointed to packaging as a key differentiator. The devices themselves are relatively simple, but require low-loss, low-noise packages with excellent thermal characteristics, he said.
Nevertheless, thermal and electric field degradation can lead to embrittlement of epoxy-based mold compounds, potentially leading to dielectric breakdown and allowing moisture intrusion, according to researcher Tina Thomas and colleagues at Fraunhofer IZM.[3]
On top of that, embedded passives make the overall package thicker. As a result, manufacturers need to worry about the rheological characteristics of the mold compound and its ability to fill the entire cavity uniformly. Silicone gel, one alternative, is thermally and chemically stable and a good insulator, but not particularly water resistant.
Researchers at the University of Maryland demonstrated a bi-layer package that combines a moisture-resistant, but rigid polyurethane layer with a mechanically compliant silicone gel. [4]
Conclusion
Heterogeneous packages blur the line between “on-chip” and “off-chip” environments. This is one reason why all contributors to the MRS Workshop emphasized the need for co-optimization of the package design and the component devices. The noise and heat characteristics and requirements of each device affect all of the others. Standardized interfaces like UCIe are a good start, but they are not a substitute for thorough simulations of proposed designs.
References
Related Reading
Advanced Packaging Makes Testing More Complex
Why 2.5D, 3D, and other advanced packaging types are driving new standards and approaches to testing.
Die-to-die Interconnect Standards In Flux
Many features of UCIe 2.0 seen as “heavy” are optional, causing confusion.
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