Advanced Packaging Picks Up Steam

The semiconductor industry’s push toward continued miniaturization and increasing complexity is driving wider adoption of system-in-package (SiP) technology.

One of the big benefits of SiP is that it allows more features to be squeezed into ever-smaller form factors, such as wearable gadgets and medical implants. So while the individual chips in this package may have less functionality integrated on a single die, the overall package contains more functionality in a smaller footprint. In effect, this is a complete electronic system in one package, with the ICs arrayed in a flat tile or vertically stacked, or a combination of both.

On top of that, SiP technology is an extension of technology that has existed for years. It’s built on existing packaging technology, such as flip chip, wafer bumping, wire bonding, and fan-out wafer-level packaging.

The multichip module (MCM) is the forebear of the system-in-package. MCMs initially were developed for data storage, such as bubble memory back in the 1960s and 1970s, and for specific military/aerospace electronics. They are still in use today in certain products, such as Nintendo’s Wii U game console. But this packaging scheme’s adoption has been limited by continuing advances in Moore’s Law, which has made it cheaper and easier to put everything on a single chip.

Fig. 1: TI’s bubble memory module. Source: Chipsetc.com

That all changed at 16/14nm, when device scaling became more difficult. And the level of difficulty continues to increase at each new node after that for a variety of reasons. At 5nm, for example, entirely new transistor structures are expected to be introduced, and new materials such as cobalt or ruthenium are under consideration as replacements for copper in the interconnects. In addition, dynamic power density and self-heating have become problematic even at 16/14nm, and they will require much more attention and advanced power management circuitry at 10nm and beyond. On the design side, as well, routing congestion has been a growing issue, exacerbated by RC delay, electromigration, and such physical effects as heat, electrostatic discharge and electromagnetic interference.

Advanced packaging provides some alternative ways of addressing those problems. First, it offers a way to minimize physical effects by utilizing physical separation. So an analog block that is sensitive to digital noise or thermal effects, for example, can be buffered more easily by using a separate chip. Second, it makes IP reuse much simpler because entire chips, or chiplets, can be re-used in a package. And third, it can improve performance and lower power by increasing the diameter of the connections between chips and shortening the distance that signals have to travel, which in turn requires lowers the power needed to drive those signals.

“SiP is in its infancy in terms of implementation,” said Yin Chang, vice president of sales and business development at ASE Group. “We’re still learning about all the possibilities of SiP. This is really the beginning of SiP.”

But advanced packaging certainly has moved beyond the basic research stage involving the viability and reliability of the various packaging approaches. Now the challenge is to achieve the same kinds of economies of scale that has provided for putting everything on a single die. The semiconductor industry has been rolling out a steady stream of options and technology developments to help that transition.

“Technical advances are two-fold,” said Chang. “One is in terms of 2.5D, where high-density silicon of various types can be connected using a silicon interposer. That allows maximum integration, and it results in a performance improvement in a small footprint. Second, putting together myriad types of functions in the past would result in chips’ conflict or interference with each other. The ability to put in dynamic shielding between those conflicting silicon performances, and putting those into a very small form factor, allows it to be used for applications that demand those kind of form-factor requirements—mostly in wearables or IoT applications.”

Fig. 2: The SiP landscape. Source: ASE

Others are making improvements to this process, as well.

“The technical advances are all about heterogeneous integration of multiple dies, as well as—and this is another key component—the effective mix and match of passives in the smallest form factor,” said Urmi Ray, senior director at STATS ChipPAC. “This is what has happened over the last few years as these patterns have emerged in the key area of optimization of passives and actives in a very small form factor. In addition, we have seen on the assembly side very efficient handling, pick and place, of small, very thin dies, and two relatively large devices. Thin dies are becoming more and more evident as, obviously, the form factors are decreasing.”

Fig. 3: A modern SiP. Source: STATS ChipPAC

Jean-Christophe Eloy, president and CEO of Yole Développement, had a similar observation. He noted that Apple’s A10 processor design, which was fabricated and assembled by TSMC, has allowed passives to move back into chip design, rather than being treated as discrete components on PCB. “Integrated passive devices are back in mobile applications, thanks to TSMC and Apple A10,” he said.

What is SiP?
Nozad Karim, Amkor Technology’s vice president of SiP/system integration, kicked off last month’s inaugural System in Package (SiP) Technology conference and exhibition in Rohnert Park, Calif. (organized by the International Microelectronics Assembly and Packaging Society) with exactly that question.

“There are a lot of definitions,” he said. “It is a system. It is a package.”

Jan Vardaman, president of TechSearch International, added more context. “The industry needs to be clear on how we define SiP, ” she said, explaining that SiP involves “two or more dissimilar die,” and “it forms a functional block.”

“SiP does not mean a single type of package,” Vardaman added. “Fan-out wafer-level packaging can be SiP.” She noted, however, that Taiwan Semiconductor Manufacturing’s InFO package-on-package technology does not fit the definition of an SiP.

Vardaman estimated that 14.9 billion SiP packages were shipped in 2016. Mobile devices, wearables, and other consumer products account for 82% of SiP implementations, Vardaman said. The market is expected to see a compound annual growth rate of 13.7% from 2016 to 2020.

The iPhone 7 and 7 Plus smartphones each have about 15 SiPs, and the Apple Watch Series 2 model contains three SiPs, Vardaman said, while the Samsung Galaxy S8 handset has 13 SiP packages.

As another point of reference, Yole Développement forecasts that through-silicon vias, which are in interposers as well as other advanced packaging, will be included in 4.5 million wafer starts in 2022 (12-inch wafer equivalents).

Fig. 4: Advanced packaging growth projections. Source: Yole Développement

Markets
Initial implementations of SiP have been in the high-end networking space, where throughput is essential and price is not a significant factor, and some of the consumer electronics and mobility markets, where the initial development cost can be amortized across high volumes and the overall price of a system.

The primary implementations today include the integration of a processor, memory, logic, and a sensor in one module, providing a one-stop solution for some customers. But as costs comes down, those offerings are expected to be especially useful to Internet of Things device developers, which are usually pressed to get the product out the door quickly.

“Modularization is a solution to allow us to create very quick time-to-market solutions,” said ASE’s Chang. “So we can use SiP in specific performances, which allows a company to put it together very quickly and get a product into the marketplace. And those are for wearables and IoT, where the market dynamic changes very quickly. Those are two divergent requirements that SiP can fulfill together.”

SiP is branching out into automotive, industrial, and medical electronics, as well, thanks to its ability to improve battery life in a smaller profile. In applications calling for high-performance requirements, such as artificial intelligence and neural engines, SiP is well-suited, as well, Chang said. “SiP can go into a broad variety of industries.” And the technology is suitable for autonomous vehicles, augmented reality, and 5G wireless communications, among other uses.

“We believe you can put it into autonomous vehicles for their neural engines, where you want to integrate high-speed processing solutions onto a very small form factor, so you don’t have a huge computer sitting on your car,” said Chang. “You are able to process at high bandwidth, so there could be an SiP for those high-bandwidth requirements, maybe 5-, 6-, 7G connection speeds with the neural engine. In that aspect, a 2.5D solution is able to provide heterogeneous silicon for those types of intensive computation needs. For augmented reality, where you want to put a display onto your glasses, the form factor becomes paramount because you really want to maximize battery life, so you don’t have to constantly charge your glasses to keep the AR going. The ability to shrink that electronics down, to modularize it quickly so you can get into the market space, also becomes critical for those customers or companies. To do those two spectra of products with SiP is very exciting for us. We’re able to do very high-density modules, leveraging all of our packaging and EMS experience, and create a solution for an AR maker. And through our bumping, our flip chip, and RDL solutions, we can create a 2.5D neural engine for the next autonomous vehicle.”

Two big benefits are RF shielding and double-sided integration of active and passive components, said STATS’ Ray. That allows double-sided printed circuit boards for mobile phones to now be shrunk down to modules.

“The modularization of functionality is really the market trend” in SiP adoption, Ray said, pointing the emerging markets of IoT, wearables, sensors, and advanced driver-assistance systems in automotive electronics. “These are very divergent markets. Heterogeneous integration is key to all of these.”

SiP is being implemented with high-bandwidth memory for wearables, which have some of the smallest form factors in consumer electronics. “The primary reason for SiP is form factor and heterogeneous integration,” Ray said.

Lessons learned
Getting to this point where SiP can even be considered as a solution has taken time, though. In fact, OSATs, foundries, and IDMs have been seriously working on these packaging approaches for the better part of a decade.

“STATS ChipPAC, like all the other OSATs, has been really focusing on developing the capabilities [of SiP],” said Ray. “The design and assembly, we have really worked hard.” The company also has turned to system-level test, combining RF testing with digital testing, to ensure that SiPs will work.

Much of this work has been collaborative, as well.

“Our greatest lesson learned is the need to closely collaborate with the customers that we work with,” Chang said. “Just because you can put together an SiP doesn’t really make an SiP solution. That close collaboration with customers, allowing them to tell you what they need both in terms of hardware, and also the software requirements, is the recipe for a successful SiP implementation. Anybody can put a Lego together. We realized that we need to work with customers to actually put the Lego block together so they can get their solution on the marketplace.”

Most of the time, the customer will supply the necessary software, although packaging houses do provide the firmware.

What’s clear, though, is that SiP technology is here to stay, and it will find much wider use in semiconductor manufacturing in years to come. With fewer companies able to follow Moore’s Law into the single-digit nanometer range, SiP presents another way forward. And as more of this technology is proven to work using off-the-shelf components, its popularity is expected to expand significantly.

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