All Roads Point Up…But When?

One of the clear messages at Semicon West this month was that stacked die are coming soon. The only question is how soon.

This isn’t so simple to answer. It depends on a lot of factors, and for most of them there aren’t any clear answers.

First of all, no one is certain what the cost equation will look like at 14/16nm, particularly once the process technology becomes more mature. There will be improvements, but certainly not on par with the area reduction gains at 28nm and prior nodes. It will cost more for double patterning, more for finFETs, and yield is still a giant question mark for complex SoCs.

This could change somewhat if EUV becomes available, but that’s a big ‘if.” EUV was expected at 40nm. The current target for insertion is 7nm, when even EUV will require double patterning. Next-generation lithography is still a work in progress, and even if it arrives in time to offset triple and quadruple patterning at 10nm and 7nm, it may not be the least-expensive option. That means fewer companies will use it for fewer chips, even though those chips will be made in high volume, which could slow the rate of cost reduction.

Second, the rate of migration to the next node is questionable. It certainly won’t be done in two-year increments by even the largest chipmakers due to investments and complexity. Double patterning isn’t as hard as triple patterning, and triple patterning isn’t as hard as quadruple patterning. Yield will suffer with each new patterning step. Moreover, derivative chips don’t span process nodes anymore, unlike in single patterning, which means chipmakers will require longer to recoup costs at each node before embarking on the next one.

Third, leveraging existing tools and technologies at older nodes—back-biasing with FD-SOI at 28nm, for example, or low-power processes at 40 and 65nm, will give new life to those nodes. This is where real cost reduction can occur for some companies, and they could leverage those older nodes with new tools and processes for years to come. Better integration of software and hardware plus new processes and techniques could buy more performance and lower power than shrinking features.

And finally, while stacked die remain a viable option—and potentially a way of leveraging all of the benefits of both advanced and older process technologies—the reality is that 2.5D and 3D still need to be proven in high-volume production. The OSATs in particular are incented to do this as a way of stopping price erosion and building back some of their profitability, and they will make a concerted push in this direction. But the time frame for when they can round up enough business to finance the investment in new equipment is still unknown.

For the most part, the tools are there, the equipment is available, and many of the bugs have been worked out of the system. Moreover, it appears that 2.5D and 3D will arrive together, instead of 2.5D serving as a stepping-stone to 3D, possibly with silicon photonics for inter-die communication. But exactly when is a matter of debate.

The good news is there is debate about this approach. The bad news is neither side has enough information to win it yet, although best guesses appear to be focused on late 2015 to early 2016. That could be revised as the calendar ticks closer, though.