Alternative Channel Materials For Post-Silicon FinFETs

At first glance, other semiconductors always have looked more attractive to device designers than silicon. Both germanium and III-V compound semiconductors have higher carrier mobility, allowing faster switching at the same device size.

And yet, as manufacturers begin to consider alternative channel materials for sub-10nm devices, the industry is remembering why silicon became a standard in the first place. It is easily doped with both donors and acceptors, allowing designers to build both nFETs and pFETs from the same material. In contrast, most alternative channel schemes being considered use germanium for pFETs and InGaAs or another compound semiconductor for nFETs. Silicon’s native oxide is a good dielectric and creates a stable, passivated surface with few defects. It is much easier to control the composition of elemental silicon than to achieve consistent ratios of the component elements in a non-stoichiometric ternary alloy like InGaAs.

Table: Carrier mobility (cm2/V-s) and lattice constants (Å) for common semiconductors. Mobility and lattice constant of InGaAs depend on the exact alloy composition.

Mobility data: Bennett, Ancona, and Boos, MRS Bulletin, July 2009.

For all of these reasons, alternative channel materials represent a radical change, forcing device makers to reconsider essentially every aspect of transistor design. This article, the first in a series examining the changes that alternative channel materials will bring, considers the device foundation—the channel semiconductor itself. While the optoelectronics industry has always depended on compound semiconductors, and SiGe source and drain regions were first demonstrated in 2002, integrating a non-silicon channel into the existing manufacturing infrastructure is something new.

The first requirement for any alternative channel material is that it be possible to deposit it onto 300 mm, and eventually 450 mm, silicon wafers. Introducing new channel materials will be difficult enough, but abandoning the silicon substrate altogether would mean developing new processes for memory, metallization, and all the other device structures that are not transistors. Moreover, silicon wafers are available in larger quantities, at lower cost, with better quality than any of the plausible alternative materials.

Still, the need for compatibility with silicon wafers imposes additional challenges, too. There is an 8% lattice mismatch between silicon and InGaAs. To achieve an InGaAs device layer with adequate quality generally requires a thick buffer and strain relaxation layer: the lattice mismatch can be accommodated by adding transitional layers with intermediate lattice dimensions, such as germanium or InP. Unfortunately, the near-interface strain drives the formation of threading dislocations, which can interfere with device characteristics well into the bulk of the material. For CMOS devices, n-type and p-type channel materials are needed, so the whole stack of strain reduction and buffer layers must be deposited and etched twice. Though devices have been made using this approach, it is probably not cost-effective for high-volume manufacturing because the metal-organic vapor phase epitaxy (MOVPE) used to deposit III-V materials is slow, and precursor gases are expensive.

Instead, IMEC has demonstrated a selective growth process, depositing germanium and InGaAs pillars into patterned oxide trenches to make a “virtual substrate” for device fabrication. Their process, described in detail here, starts by using standard shallow trench isolation processes to create a template, with pillars of silicon surrounded by silicon dioxide. Then, a silicon dioxide cap is deposited over the areas where InGaAs will ultimately go. In the uncapped regions, the silicon pillars are etched away, and the exposed trenches filled with germanium. Next, the germanium is capped with silicon dioxide and the InGaAs areas are exposed.

InGaAs pillar formation begins by etching out the silicon pillars to create a concave bottom surface, slightly wider than the ultimate trench width. Successive depositions of germanium, InP, and InGaAs follow, gradually accommodating the lattice mismatch between silicon and InGaAs. The narrow trenches are key to this process: because of the rounded bottom surface, dislocations tend to form at an angle to the sides of the trench, and are trapped against the sidewalls rather than propagating through the InP and InGaAs bulk. An active layer with acceptable quality is achieved with a thinner, less time-consuming deposition. Moreover, with selective deposition there is no need to etch InGaAs, or to dispose of toxic arsenic-based etch by-products. Using this technique, IMEC recently demonstrated what it believes to be the first III-V FinFETs integrated epitaxially on 300mm silicon wafers.

Figure: Bright field cross-sectional TEM images of InP in 100 nm and 200 nm wide trenches, showing threading dislocations trapped at the bottom of the trench. Image courtesy IMEC, from Waldron et. al., ISTDM 2012.

Much work remains to be done, though. Aaron Thean, director of Logic R&D at IMEC, noted that the choice of dielectric materials is extremely important. The gate dielectric must provide the appropriate energy band structure, but must also give a clean interface that minimizes interface traps, and must resist diffusion from the semiconductor. According to Nadine Collaert, IMEC’s manager of III-V and germanium R&D, the gate dielectric may need to consist of more than one layer, such as an AlO2 diffusion barrier combined with a thicker HfO2 layer. The thermal budget will need to be extremely low: both indium and arsenic are mobile diffusers at temperatures as low as 500 – 600 ºC. A gate last design may be needed to give manufacturers more flexibility.

The next installment will focus on the interfaces between alternative channel materials and the gate dielectric.