Alternative To x86, ARM Architectures?

Support grows for RISC-V open-source instruction set architecture.


Software developed by professors and graduate students from the University of California at Berkeley? That will never fly in the semiconductor industry, right?

Maybe they said that about SPICE, four decades ago. The jury is still out on RISC-V (pronounced risk-five) the modular, open-source instruction set architecture created in this decade by Cal professors and students, yet the ISA is gaining the support of heavyweight companies in computers and software.

Krste Asanovic, a UC Berkeley professor who also serves as chairman of the RISC-V Foundation, made a presentation on the ISA in a “Sky Talk” (as in “blue sky”) at the 53rd annual Design Automation Conference in Austin, Texas.

ISA functions as the interface between computer hardware and software. “Most important interfaces are not open source,” Asanovic noted. The most widely used are the x86 architecture created and maintained by Intel, and the architectures developed by ARM Holdings.

Intel has jealously guarded its x86 architecture for decades. Although it once struck a licensing agreement with Advanced Micro Devices allowing AMD to serve as a second-source supplier of x86-compatible microprocessors, the companies later engaged in a protracted legal battle over what AMD could do under that license before more recently reaching a legal settlement and cross-licensing agreement. AMD’s licensing deal with a Chinese semiconductor company threatens to heat up more contention between the longtime rivals, however.

Asanovic joked that the shortest unit of time is not the moment between a traffic light turning green in New York City and the cab driver behind the first vehicle blowing the horn; it’s someone announcing that they have created an open-source, ARM-compatible core and receiving a “cease and desist” letter from a law firm representing ARM.

Setting out in 2010 to develop an open-source ISA as a summer project with Berkeley colleagues, Asanovic said a three-month project extended over four years, reaching a frozen base user specification in 2014. During those four years, the RISC-V team was astounded to get inquiries from the world, asking why the spec was being changed in classes at the Cal campus. This added an impetus to freeze the basic ISA code.

“It took a lot of work to make it this simple,” Asanovic noted.

The RISC-V Foundation was formed as a not-for-profit organization that could handle trademarking the ISA and provide a structure for worldwide use of the architecture. Corporate members of the foundation include BAE Systems, Google, Hewlett Packard Labs, IBM, Microsemi, Nvidia, Oracle, Rambus, and Western Digital.

SiFive, a startup founded by the original developers of RISC-V, is a founding member of the foundation, with a “Platinum” level of support.

A recent report by Rambus and the Global Semiconductor Alliance hailed RISC-V as “the ‘Linux’ of microprocessors.”

Asanovic concluded his DAC talk saying, “Free and open architecture – and it’s good!”


Karl Stevens says:

There are/have been many, many RISC architectures and they boil down to many addressing modes for loads and stores to load operands into registers and to store results. RISC-V is another variation.
The real key is the memory/cache/prefetching/branching.
Further heterogeneous(AMP) is evolving and actual computation is key so computation loops and pipe-lined expressions is more important.
True RISC would do if/else, for, while, do, and assignments.

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