An Introduction To Virtual Semiconductor Process Evaluation

Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process engineering problems cannot be solved with a brute force, step by step approach to understand every cause-and-effect relationship. There are simply too many process recipe variables that can be modified to make a brute-force solution possible, given limited time and resources. Process engineers typically use statistical methods and correlation analysis on a limited sample data set to accelerate their understanding of process changes. However, when performing wafer-based testing, even a very small DOE (design of experiments) can take days to reach a simple conclusion, due to the time needed for wafer preparation, equipment assignment, measurement and TEM analysis. With a large wafer-based DOE, the time to solution can turn into weeks and even months. Using a proper “virtual process” library and virtual fabrication techniques, it is possible to achieve similar results within hours or days at a much lower cost.

1. Testing a new process recipe in an actual semiconductor fabrication facility
Once a device is in manufacturing, a process engineer cannot quickly change a process recipe, since new process recipes need to go through specific qualification procedures. Even though an engineer thinks that there is a better process recipe for a specific process step, the engineer needs to test the reliability of any new recipe with respect to equipment contamination and process repeatability before it can be used in production. To ensure manufacturing stability, a tool chamber might need to produce wafers using the new process recipe for at least a one cycle preventive maintenance period. In practice, this means that a new recipe may not be able to be used for at least a week, since engineers can only use qualified recipes on qualified chambers.

Fig. 1: Normal estimated procedure for chamber condition transition.

Even qualified recipes may need a “warm-up” before transitioning to manufacturing, in order to optimize the chamber environment (see figure 1). An engineer might need to wait for over a day to see measurement and SEM / TEM analysis results from wafers produced on the chamber. If the chamber went through any process changes to optimize the chamber conditions, additional warm-up time will be needed to get the chamber back to its original condition and continue production.

When an engineer is testing a new process recipe, costs such as chamber downtime, the cost of silicon wafers, metrology, process consumables (like gas), PVD targets, electricity, analysis time and engineering hours are sometimes hidden and are not always fully recognized by the engineer.

2. Testing a new process recipe in a virtual fabrication environment (software modeling)
The biggest difference between testing a process on real world equipment compared to testing it in a virtual fabrication platform is the consistency of the test environment. The test environment in the real-world varies considerably, as the conditions on the chamber (or tool) change. These changes are dependent upon the process material and process power in use. In a virtual environment, there is no degradation of the chamber and no time dependency, even under varying process conditions. The virtual environment is completely consistent across process test conditions. An engineer simply needs to prepare a process library and define the initial incoming base or test structure, in order to obtain his or her expected test results (see figure 2).

Fig. 2: Simulation/emulation procedure on test structures using pre-defined process libraries.

No matter what incoming structure is provided by a user, the simulation engine will produce an accurate output of the device based upon the theoretical, calibrated behavior of the actual manufacturing processes performed. Engineers can evaluate new process concepts on various structures at their discretion. If an engineer has a pre-defined process library, and subjects a structure (silicon device) to a set of test processes, virtual fabrication can help the engineer understand the relationship between any input process parameters (or settings) and the final device output, since all test results can be quantified using virtual metrology.

3. Example of a process recipe test using virtual fabrication
Let’s look at a scenario where an engineer needs to evaluate an etch process on three different test structures, during the evaluation of potential process schemes for a new device. The etch module consists of two etch process recipes, and the engineer has already obtained the analysis results from the first etch process (see figure 3).

Fig. 3: Incoming structure after first etch process

In our scenario, the engineer needs to verify that his second etch process recipe can produce a flat bottom surface on the device (after the first etch step is complete) without creating residues on this bottom surface. Fortunately, this engineer has a second etch process library built into process modeling (or virtual fabrication) software. The library is well-calibrated to actual silicon data and it has already proven that it is a predictive (in other words, it can produce accurate simulation results for this second etch process). In this case, all the engineer needs to do is execute a simulation of the second etch process on the previously defined structures of interest.

Fig. 4: Simulation result of a specific etch process library on three different structures. (A) Left, (B) Middle, (C), Right

The engineer could then produce simulation results within a few hours (figure 4) showing the expected results of the second etch process. Very quickly, the engineer would learn that only one of three incoming structures could produce a relatively flat and uniform bottom surface without residue (see figure 4B). This study could also be extended toward further development of the second etch process, to determine modifications needed to the second etch process parameters to improve (flatten) the bottom profile on the two remaining test structures (figures 4 A&C).

4. Process engineer’s expanded utilization of simulation software
As TCAD software has become easier to use, we have also seen virtual fabrication software expand to the process engineer’s domain. Process engineers have always generated reliable data from controlled process tests, using their well-earned knowledge about processes, chambers, and equipment. Using this knowledge, they can easily understand the process model behavior built into virtual fabrication software and can link these process models with TCAD and CAE models to highlight the effect of a process change on device or circuit level behavior. With virtual fabrication models and calibrated process libraries, process engineers can obtain expected results from a process change in a few short hours, without the costly time and expense of wafer-based testing.