Architecture First, Node Second

What a difference a node makes.

A couple of rather important changes have occurred in the move from 16/14 to 10/7nm (aside from more confusing naming conventions). First, companies that require more transistors—processor companies such as Intel, AMD, IBM and Qualcomm—have come to grips with the realization that they can pack more logic onto a die, but they can’t access those transistors as easily as in the past. And second, most have concluded that shrinking features alone is no longer good enough for achieving 35% or greater improvements in performance and/or power. So while the industry will continue shrinking down to 7 and 7+ (yet another confusing number), the real focus has shifted to the architecture.

That architecture is only partly about the on-chip logic, which is the data processing piece. The underlying shift involves changes in the flow of data. Systems are becoming more distributed—think about the sensors in a car, for example, or a cloud versus a classic data center—and processing of data needs to happen wherever it can be done fastest, cheapest, and using the least amount of power. That often isn’t a single-chip solution, in part because it takes power to move large amounts of data and in part because not all data types are the same. Video data is different than text, for example.

This is why there is so much attention being paid to interconnect standards such as Gen-Z, CCIX, OpenCAPI, and to new memory types (ReRAM, 3D Xpoint, phase-change), which can help reduce latency.

“With EUV coming, we’ll get to 7nm and 5nm,” Venu Venugopal, vice president of engineering in Cisco’s Core Software Group, said during a panel at this week’s GSA Silicon Summit 2017. “But architecture, by far, moves the needle the most.”

So while scaling is still important to companies developing big logic chips, scaling alone doesn’t determine when companies will migrate to the next node. It depends on a variety of factors, and those myriad factors will becoming increasingly important over time. The commonly used term these days is “balance,” and it involves such things as memory architecture and access, on-chip and off-chip bandwidth, and single-chip or multi-chip configurations.

“If you’re trying to get performance from just one place, it’s not going to scale,” said Joe Macri, corporate vice president and product CTO at AMD said. “We’re talking about distributed memory, memory hierarchy, computing on the edge—all of this is distributed computing.”

Craig Hampel, chief scientist for Rambus‘ Memory and Interface Division, agrees: “Moore’s Law is going to slow because if you have 64 or 48 cores, you can’t use them all. It may be better to reduce the higher-transistor count to include application-specific acceleration. We are seeing instruction sets from companies like Intel for security and compression, for example. We’re seeing GPUs getting integrated, and even FPGAs. So we’re looking at application-specific or data-specific resources as opposed to just replicating a structure.”

This doesn’t necessarily mean fewer transistors. In fact, ultimately it may require more transistors. But they don’t all have to be on one chip.

“You need to get to shared efficiency,” said Nick Ilyadis, vice president of portfolio and technology strategy at Marvell. “It doesn’t all have to be on the same chip. It can be on multiple chips. But with heterogeneous systems, the more you break things up, the more transistors you need.”

This is a fundamentally different way of approaching the problem, and in the past this kind of thinking was not an option. At 28nm, adding another chip added to the cost. At 16/14nm, though, the formula changed. The price per transistor, or even the cost per watt, is no longer cheaper. And at 10/7nm, doubling transistors not only isn’t less expensive, it’s more time consuming to design and manufacture.

So while shrinking remains an important option for logic, it’s only one piece of the solution after 16/14nm.

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