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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

The Evolution Of High-Level Synthesis
By Brian Bailey - 27 Aug, 2020 - Comments: 3

High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Redefining The Power Delivery Network
By Brian Bailey - 13 Aug, 2020 - Comments: 3

Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

The Evolution Of Digital Twins
By Brian Bailey - 03 Aug, 2020 - Comments: 1

Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Engineering Within Constraints
By Brian Bailey - 30 Jul, 2020 - Comments: 0

One of the themes of DAC this year was the next phase of machine learning. It is as if CNNs and RNNs officially have migrated from the research community and all that is left now is optimization. The academics need something new. Quite correctly, they have identified power as the biggest problem associated with learning and inferencing today, and a large part of that problem is associated with ... » read more

Open-Source Verification
By Brian Bailey - 30 Jul, 2020 - Comments: 1

Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

A Virtual DAC Experience
By Brian Bailey - 24 Jul, 2020 - Comments: 0

This has been the first virtual conference for me, and I will say I was not sure what to expect. I did moderate a panel for it, but that was pre-recorded because the panelists did not care to be awake and performing live for what would have been 3 a.m. for them. I hosted a virtual happy hour, I conducted many interviews, attended sessions, keynotes and other events, but one thing stands out to ... » read more

Vtech: Bus Performance, FPGA Debug
By Brian Bailey - 15 Jul, 2020 - Comments: 0

It has been a long time since I was able to talk about a new verification company, but today I can introduce you to Verification Technology, or Vtech for short. If you do a search for them, you will probably find a company that sells baby monitors and kids toys. This is not that company. So, let's make sure you have the right web address to start with https://vtech-usa.com/ or https://vtech-inc... » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Designing For Extreme Low Power
By Brian Bailey - 09 Jul, 2020 - Comments: 3

There are several techniques available for low power design, but whenever a nanowatt or picojoule matters, all available methods must be used. Some of the necessary techniques are different from those used for high-end designs. Others have been lost over time because their impact was considered too small, or not worth the additional design effort. But for devices that last a lifetime on a si... » read more

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