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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Who’s Responsible For Security Breaches?
By Brian Bailey - 24 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

Disregard Safety And Security At Your Own Peril
By Brian Bailey - 10 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

DAC 2019: Day 3
By Brian Bailey - 06 Jun, 2019 - Comments: 0

Two keynotes get day three of DAC started. The first by John Cohn, Massachusetts Institute of Technology & IBM Watson AI Lab. "I am a nerd. Look back 100 years in processing. We have gone from mechanical computing to where we are today, but it has not been a smooth curve. There are smooth places and then discontinuities. This is when what you were working on no longer works. How we make tho... » read more

DAC 2019: Day 2
By Brian Bailey - 05 Jun, 2019 - Comments: 0

Day two of DAC started off with a highly anticipated keynote given by Thomas Dolby, musician, producer and innovator. Dolby has always been fascinated with the convergence of music and technology. He started off with a fanfare by balancing a broom on his finger to demonstrate the type of control we have as human beings. He went on to expand the analogy to the hive mind of groups of individuals,... » read more

DAC 2019: Day 1
By Brian Bailey - 04 Jun, 2019 - Comments: 2

The last time that DAC was in Las Vegas was 2001. Much has changed since then. The first day kicked off with the usual ceremonies and then two short keynotes. A change from previous years is that keynotes are now on the show floor. This is presumably to ensure that once the keynotes are over, everyone sees the vendor booths. During the commencement session, it was also announced that all cof... » read more

Moore Open Source Coming
By Brian Bailey - 30 May, 2019 - Comments: 0

The sunsetting of Moore's Law is creating some interesting ripples throughout the EDA and IP industries. No longer is the low-risk path defined by a migration to the next node. Most companies cannot afford it and don’t need it. Neither can their competitors. Suddenly, they have to do more with less, or at least the same amount. Consider just a few things that are changing today: Stick... » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

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