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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Power Management Heats Up
By Brian Bailey - 14 Apr, 2016 - Comments: 0

Power management has been talked about a lot recently, especially when it comes to mobile devices. But power is only a part of the issue—and perhaps not even the most important part. Heat is the ultimate limiter. If you cannot comfortably place the device on your face or wrist, then you will not have a successful product. Controlling heat, at the micro and macro levels, is an important asp... » read more

Bridging The IP Divide
By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 06 Apr, 2016 - Comments: 3

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro Riz... » read more

A Formal Transformation
By Brian Bailey - 24 Mar, 2016 - Comments: 0

A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

An Unsustainable Divide
By Brian Bailey - 24 Mar, 2016 - Comments: 0

One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

IP Risk Sharing
By Brian Bailey - 10 Mar, 2016 - Comments: 0

For most people within the semiconductor industry, managing risk involves making the right product decisions that will enable a company to be profitable, and ensuring the product is successfully produced within the necessary time window. In contrast, for products within high-risk areas such as medical and mil/aero, design often proceeds at a slower pace, using proven technologies and adopting l... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

IP Requirements Changing
By Brian Bailey - 25 Feb, 2016 - Comments: 0

Twenty years ago the electronics industry became interested in the notion of formalizing re-use through third-party IP. It has turned out to be harder than anyone imagined. In 1996, the Virtual Socket Interface Alliance ([getentity id="22845" comment="VSIA"]) was formed to standardize the development, distribution and licensing of IP. Soon afterward, companies with a couple of people in a ga... » read more

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