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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Tech Talk: 10nm Patterning
By Brian Bailey - 20 Aug, 2015 - Comments: 0

David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics, talks about triple and quadruple patterning after 20/16/14nm and what design teams need to understand to get this right. [youtube vid=7bjutPWakpw] » read more

Intel Acquires Docea Power
By Brian Bailey - 14 Aug, 2015 - Comments: 0

Intel has quietly done another EDA acquisition, this time buying Docea Power, a small company based in Moirans, France. Docea had high-level power and thermal estimation tools. The acquisition closed July 31st. [getentity id="22222" comment="Docea Power"] was founded by two brothers, [getperson id="11137" p_name="Ghislain"] and [getperson id="11138" p_name="Sylvian"] Kaiser. Ghislain had spe... » read more

DVFS On The Sidelines
By Brian Bailey - 13 Aug, 2015 - Comments: 2

Power reduction is one of the most important aspects of chip design these days, but not all power reduction techniques are used equally. Some that were once important are fading and dynamic voltage, and frequency scaling (DVFS) is one of them. What's changed, and will we see a resurgence in the future? What is it? DVFS has physics powerfully in its favor. As Vinod Viswanath, director of res... » read more

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

Securing EDA In The Cloud
By Brian Bailey - 30 Jul, 2015 - Comments: 1

In the first part of this article, EDA’s Clouded Future, the types of application suitable for cloud-based solutions were examined and the cost benefits that could arise for both EDA suppliers and consumers. Security has stood in the way of widespread adoption, but it is a little more complex than just being concerned about a theft of sensitive design data. Security involves data protect f... » read more

IP Verification Challenges
By Brian Bailey - 30 Jul, 2015 - Comments: 0

At the Design Automation Conference this year, the Designer and IP tracks were the stars of the show in many ways. These sessions catered to industry rather than academia and provided engineers with information they could directly use in their jobs. Many of the sessions were filled to capacity and Anne Cirkel, general chair for the 52nd DAC, was enthusiastic about the growing success of these t... » read more

Technology Tsunami Approaches
By Brian Bailey - 27 Jul, 2015 - Comments: 0

How many times have we heard the saying that technology advancements are accelerating and that inevitably the older generation will have increasing problems keeping up with the new advancements? This happened to me with software development methodologies over fifteen years ago. I still program, when people actually let me, using basically the same techniques I learned when I was in my teens.... » read more

Moore Memory Problems
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

Tale Of Two HLS Viewpoints
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The Design Automation Conference attracts several co-located conferences, symposiums and other such gathering of people, often on more specialized topics than would appeal to the general DAC attendees. Some of them are more research-focused, but one conference is somewhat strange in that it is about a subject that has transitioned to commercial tool development and yet still remains an active a... » read more

EDA’s Clouded Future
By Brian Bailey - 25 Jun, 2015 - Comments: 0

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

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