Running rule checks for designs that target FPGAs from Xilinx, Intel, or Microchip with minimal setup.
Aldec’s ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware.
The solution supports running rule checks for designs that target FPGAs from Xilinx, Intel or Microchip with minimal setup. It also offers the latest versions of FPGA vendor libraries, which are pre-built, installed by default, and pre-configured for advanced timing and CDC rule checks.
To help FPGA designers, ALINT-PRO provides automated project conversion from the most popular FPGA design environments — Xilinx Vivado and Intel FPGA Quartus. ALINT-PRO automates the import of a projects code into the native ALINT-PRO environment, whereas the automated project conversion functionality helps the designer prepare and run static verification of FPGA projects in ALINT-PRO. As part of the conversion, workspaces and projects are created and populated with code and settings, allowing designers to immediately run static code verification.
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