Backside Power Delivery Adds New Thermal Concerns

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices.

While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substrates. Today, Intel and imec have proposed separate backside power configurations. Each comes with pros and cons, and both add new challenges.

“There are concepts in which each standard cell is connected to the backside power grid via TSVs,” said Andy Heinig, head of department for efficient electronics at Fraunhofer Institute for Integrated Circuits IIS‘ Engineering of Adaptive Systems Division. “In this case, the reliability of the power grid is critical, as failures of individual TSVs can lead to malfunctions of the entire system. But these concepts require TSVs with a very small diameter, which leads to TSVs with a poorer yield.”

Using larger TSVs, which might seem to be an obvious solution, leads to a mixture of power/ground layers on the back, as well as on the front. “The disadvantage is that such concepts block some routing resources on the frontside,” said Heinig. “As a result, such concepts cannot realize the entire power of the backside power delivery. Energy-saving concepts require certain different power/ground structures that are isolated from each other, but also require active transistors to switch the power grid on and off. Such active devices are only present on the frontside, which means that different connections are required between the front and backside.”

From a larger system perspective, the chip is going to look similar regardless of how the power is delivered to the individual transistors. “For example, all the pin-outs are going to look the same, so the system designer doesn’t have to do anything to get the benefits,” said Eric Fetzer, an Intel fellow. “In terms of system impacts, when the losses are improved right on the silicon, the other losses in the system have a more significant performance bottleneck. If it was X% from the wall to the regulator, X% from the regulator to the CPU, and X% on the CPU, I’ve now just taken that X% on the CPU and improved it, so the other two items become the problem pieces of the pie. Thus, by reducing some of the losses on-die, you now want to focus on improving the losses off-die because your return is bigger for that.”

The industry has been buzzing about backside power delivery for nearly five years, starting with early proposals from Intel, now called PowerVia, and imec’s buried power rails research. To enable that shift, EDA vendors have been updating their tools to handle backside power designs, while making sure the interfaces will be comfortably familiar for design teams.

“In terms of the look and feel, designers won’t see anything different, other than some backside power-related options,” said Augustine Weaver, senior staff solutions engineer, EDA group at Synopsys. “There are a couple of disruptive things that users need to understand to get started. For example, what collateral is different to support a backside PDN? What kind of layers do you have? What are the characteristics, the widths, pitches, and new design rules that may come from backside layers? You need to create a realistic area floorplan to do the placement and routing of the cells. You could have multiple power domains that will have a huge impact on how you build your floorplan.”

Fig. 1: Increase in signal access points with a backside PDN. Source: Synopsys

In other words, backside power delivery fundamentally breaks the assumption that all routing layers are on the frontside of the die. Still, this isn’t a trivial change.

“We know it can be done, but it leads to a snowball effect,” said Rod Metcalfe, product management group director at Cadence. “Yes, we can route nets on the backside of the die. But we also have to extract those nets. If you want to analyze the power delivery network, you need to do an IR drop analysis, which needs parasitic information, and that comes from the extraction engine.”

This means the extraction engine has to be enhanced for backside routing layers, as well as the analysis engine, so it can accurately perform an IR drop analysis that considers the backside layers. “Everybody thinks the big change is routing on the backside, but that actually creates a series of other changes that EDA had to consider,” Metcalfe said. “So there has been quite a lot of work from the implementation flow to enable these sorts of technologies.”

Rethinking standard cell design
While EDA tools may account for backside power, standard cell libraries also will need to be updated, Metcalfe noted. “If you stick with the current standard cell libraries of today, those have the power rails on the frontside. And those power rails tend to be on metal-1 and metal-2. To connect frontside to backside, foundries use through-silicon vias. Thus, if you’re using your existing standard cell library, you will need to create special cells that contain TSVs, and those special cells will need to be placed correctly so they can connect to the power rails or the standard cells themselves.”

Alternatively, a designer could use the buried power rail approach. “In this version, rather than having the power rails on the top of the standard cells, they are buried deep inside the standard cell,” he explained. “Then you can connect from the power, which is on the backside, directly into the buried power rail, and you don’t need to go all the way up to the upper metal layers. That has some density benefits, including connecting to the power more efficiently. In that case, you have to completely redesign the standard cells. Users who want to gain access to backside power very quickly tend to use the existing standard cells with additional TSV cells. The placement engine inside the implementation tool needs to understand this, so it can place these TSVs cells in a regular pattern to connect the power from the backside to the frontside. Alternatively, the standard cells can be redesigned with buried power rails, but that is a much larger undertaking.”

Lack of shielding: A potential issue
Many people are concerned that a backside power approach could take away the traditional design advantage of using power and ground structures to shield very sensitive nets, such as protecting a clock net from adjacent signal nets. “That is very easy to do when you’ve got power on the frontside, because you have many local connection points to the power grid that’s on the frontside,” Metcalfe noted. “On the backside that becomes very difficult, because you don’t naturally have access to the power to connect the shield wires to some localized power connection. You have to think very carefully about how to connect to those power structures from your shielding wires. By contrast, that is very trivial to do when you have frontside power.”

By contrast, Eric Beyne, senior fellow, vice president of R&D, and program director for 3D System Integration at imec, said this may not be much of a problem after all. “Since the backside is the new frontside, you could say that signals are running internally in the chip further away from this new frontside, so shielding won’t be less effective,” he said. “That doesn’t mean there will be no metal lines for reference voltage on the frontside. They would not be carrying all the power to deliver to the devices, so it’s a bit different. You can still have a shielding metallization on the frontside, as well, but it will be internally in the chip, not to the external world.”

Thermal challenges
While the effect of backside power on shielding is debatable, it won’t solve thermal problems, and it may exacerbate them.

“Thermal management is always a problem, and will likely become even more of a challenge,” said Marc Swinnen, director of product marketing at Ansys. “Backside power can change the whole thermal picture. Heat can now more easily escape from the bottom of the chip rather than the top, so chips with backside power need to be flipped for mounting. Possibly more significant is that backside power allows a tighter packing of standard cells, since there is now more routing resource available. This is great for cost reduction, but it also has the effect of increasing the power density of the chip, which makes thermal worse.”

Extreme heat differences between frontside and backside designs are another reason for re-thinking traditional approaches to design when using backside power delivery.

“The heat generated on the backside of the silicon turns out to be 2X or even more compared to the older technology,” explained Lang Lin, principal product manager at Ansys. “In the past, your design probably reached about 50ºC. Now you could get to 100ºC. The bottom of the die could get so hot that it could kill the whole die. In addition, that kind of heat can cause electromigration problems, which will affect reliability. The power of the whole system needs to be reduced as much as possible to reduce the heat, but that’s not the ultimate solution. Given situations where the power cannot be changed, you have to do thermal-aware place-and-route to optimize the system. The ideal is to make the heat evenly propagate throughout the whole area, so there’s not a single point that can become a hotspot.”

Intel’s Fetzer said the reverse is true for electromigration effects. “It’s actually a much easier problem to solve. PowerVia makes most of that electromigration reliability easy to meet. In fact, from a designer’s perspective, we have so much grid — and the grids are so short, only a few layers deep, that we actually don’t run into the problem that you’d normally have with very high currents through very sparse metal. Because I connect at a device level to this large grid, I end up with no reliability errors when I’m putting the system together, as opposed to having to be very careful about managing the current through vias and wires in what would normally be a signal interconnects stack.”

Backside power requires multi-physics simulation as well as an understanding of mechanical engineering earlier in the design flow. For example, the thermal coefficients of different materials need to be considered in the context of mechanical stress, because the effects can be different in the X, Y, and Z directions.

“The intense scrutiny focused on chip cooling has also led us to refine the thermal modeling for the other chip layers,” said Swinnen. “Heat likes to travel along the metal interconnect wires, and on some interconnect layers the metal is all vertical, while in others it’s all horizontal. Each layer has a very anisotropic thermal conduction, so these chips don’t conduct heat the same way in both directions. This makes a difference when you are pushing thermal optimization as much as possible.”

Still, designers have to be conscious about the density of the circuits — more watts per millimeter squared, or more power per unit of area. “Be aware of the density of your circuits and the amount of power you’re burning in a particular space,” Fetzer said. “The more you can do to spread that out, the better your design will be. In the past, your silicon was your radiator, where you pulled the heat out. In a PowerVia design, there is very little silicon, so you have to be aware of what’s bringing the heat out of the system. You need to make sure that your copper wiring, etc., are designed in a manner that assists in the removal of heat from the system.”

The potential of multiple domains
Backside power also opens up the possibility of denser and more compact designs, where signaling, as well as power, can be moved around the chip as needed.

“It’s worth it for designers to spend the effort to understand this technology because there is absolutely no reason why you can’t put signal routes or clock routes on the backside of a chip,” said Cadence’s Metcalfe. “In the future, designers will have a lot more freedom.”

Switching power to the backside could be just the start of an entire rethinking of chip design. “If you talk to designers, there’s never enough sides of the chip,” imec’s Beyne said. “If you provide the power on the backside, you can provide more decoupling on the backside, lower RC, and other features that are beneficial for the performance of the chip and you have more freedom to have more domains. Long-range functionalities that are not overly localized could move to the backside as well to save space. It’s not necessarily limited to logic, because there’s also quite a lot of partitioning inside memory devices, for example, maybe bit lines and work lines that connect to the periphery chip could be possible.”

Fig. 2: Backside PDB increases wire density through improved layer assignments and signal routing. Source: Synopsys

Finally, there will also be additional PPA flexibility for designers. “With buried power rails, the cells can be a little bit bigger because the buried power rail is not under the active device, whereas in a PowerVia design, the power can come directly under the active gate,” said Synopsys’s Weaver. “This has a direct impact on the size of the standard cell in terms of the width, number, and height. Now that the pins are in the backside, height is no longer the size-limiting factor for frontside cells. The cell size can be reduced, allowing more cells to be packed closer, and therefore the density can be increased, directly helping to reduce the core chip area.”

Fig. 3: imec’s buried power rail approach. Source: imec

Fig. 4: Intel’s PowerVia, with image at left showing power and signal wires intermingled at top of wafer, and image on right showing PowerVia backside power delivery network. Source: Intel

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