Breakthrough approach delivers better scaling and power efficiency, but at the cost of new processes like wafer thinning, bonding, and advanced debug.
Backside power delivery is being called a game changer — a breakthrough technology and the next great enabler in CMOS scaling.
It promises significant PPA advances, including faster switching, lower voltage droop, and reduced power supply noise. And it is poised to deliver these benefits below the 2nm node, despite a substantial disruption in front-end processes from lithography pattern distortion caused by extreme wafer thinning, wafer bonding, and multi-layer process stacks on the frontside.
Despite those challenges, the leading foundries are making progress. Intel currently is ramping yield at its 18A node with its PowerVia technology. TSMC expects to implement its Super Power Rail technology for HPC applications at its N16 node in 2026. And Samsung is working on BPDN technology, although it has yet to disclose a production timeline.
Backside power delivery relocates power to the back of the wafer and leaves only signals to be transmitted through frontside interconnects. At a fundamental level, it is about directly delivering power to where it is needed.
“You want to deliver better power to the transistors,” said Eric Beyne, senior fellow, vice president of R&D and program director 3D System Integration at imec. “So rather than running power up through a back-end-of-line stack of 15 layers in kind of waterfall fashion, with high impedance and resistive losses, we actually put the power supply below in close proximity to the transistors. That more effectively decouples the front-end devices.”
The clever separation of the power delivery network from data delivery is especially beneficial to high-performance computing (HPC) devices. Here, backside power addresses the increasing problem of parasitic voltage (IR) drop, which drastically reduces product performance and gets worse with each process node. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient frontside approaches, backside power delivery networks (BPDNs) reduces power losses by up to 30% due to less voltage droop. The silicon frontside interconnects are freed up for routing signal interconnects only, and can even lower cost due to fewer expensive EUV lithography steps.
“There’s a large cost benefit to just going to backside power, because the biggest driver for cost is litho passes” said Kevin Fischer, vice president, director of interconnect and memory technology integration at Intel. “And if you push a pitch beyond its breaking point, you have to switch, for instance, from 193nm immersion to EUV, or from EUV to a pitch doubling scheme. We are going all direct print on the frontside and do not need to do pitch division, meaning one pass for trench and one pass for via at all layers. You still have to add layers to the backside, but these are coarse metal lines a couple hundred nanometers thick, so they are relatively inexpensive.”
Nonetheless, backside power brings entirely new tooling into fabs, such as wafer grinding systems to thin the silicon wafer dramatically (to <100nm) along with wafer-to-wafer bonding systems. “There’s a lot of new tooling involved such as wafer bonding and wafer grinding, which are not normal in the semiconductor industry,” said Fischer. “And then you’ve got to do front to back alignment. These are not processes we’ve done before.”
In addition to mastering these processes, backside power delivery introduces altogether new stress profiles that must be managed. For example, the thermal expansion mismatch between different materials used in the backside metallization and TSVs generates mechanical stress, potentially affecting transistor characteristics. Using virtual fabrication, a recent study by Lam Research’s Semiverse Solutions team revealed that backside direct connect schemes exert significant additional stress to gate-all-around transistors relative to traditional frontside connection schemes. [1]
The move to backside power substantially impacts design as well as manufacturing. “One big benefit is the fact that you’re freeing up a lot of routing resources that would normally be taken up by power,” said Jim Schultz, senior staff product manager at Synopsys. “But making use of all that additional signal routing takes a lot of retooling from the EDA side, because we’ve been doing it one way for decades — trying to maximize the efficiency of power and signal routing together. This is a big change.”
The flip side is there are more routing options. “There is an additional degree of freedom that should make it easier to solve problems because you just have a lot of routing resources,” Schultz noted. “For instance, you can reduce cross coupling by doing double spacing between wires. That can help the electromagnetics. If I have two signal wires running next to each other, I can split it up and go from metal 3 to metal 5 and back down in sort of a horseshoe pattern. So there are new options available.”
Others agree. “On the design side of things, there’s a pretty big benefit,” said Fischer. “We see the ease of use of routing tools is improved because they can operate without tripping over the power grid. And because we can direct print all the metal layers, we don’t have to deal with pitch division rules, which tend to be very complicated.”
More direct power delivery also leads to better utilization of power. “The density of active transistors can scale much better by having better power utilization,” said Intel’s Fischer. “Power utilization, which is driven by the power that can reach each cell, leads to more effective utilization of the transistors on the wafer. We achieved about a 10% utilization gain with backside power versus without backside power.”
The backside power delivery scheme provides a one-time relaxation of metal pitch on the frontside, which may be instrumental in delaying for a node or two any replacement of copper interconnects with a lower resistance metal, such as ruthenium at the fine-pitch layers.
Fabricating vias and silicon wafer thinning
As with any game-changing technology in semiconductors, there are substantial hurdles to overcome to prove out new process recipes, perform the yield ramp, and then ramp it in high volume production. For backside power these include:
Fig. 1: The transistors and power via are fabricated first (a), followed by multi-level frontside metallization and dielectric seal (b), bonding to silicon carrier (c), then backside power processing. Source: Intel
These processes become increasingly more difficult with advanced backside power delivery schemes, of which there are three. The first, called BPDN with power rail, essentially connects vias from a backside power rail up and around the CMOS FETs and down through the top contact. Initially developed by imec in 2019, the power rail approach is the least disruptive to the front-end device flows.
The second approach, generally called power via, is a slightly more complex approach that forms the via from the frontside to the frontside contact, achieving more scaling benefits than power rail. Intel’s process flow for PowerVia (see figure 1), has been in development for about 10 years.
The third approach, direct connect, is the most challenging to implement, but it also delivers the greatest performance and scaling benefits. In this scheme, backside vias directly contact the transistor’s source or drain from underneath, meaning wafer thinning and etching is performed until there is almost no silicon substrate (10nm) remaining.
Imec has explored direct connect schemes for the last several years. “Our backside power delivery scheme has evolved in CFET and nanosheets to direct contacts,” said Beyne. “The idea is to contact the source/drain directly on the back, which means you have to tighten all the tolerances to do that effectively. With our initial backside power scheme and initial TSVs, if you have 20nm overlay in the lithography after all the distortions, that works. But if you contact the gates, for instance, you need overlay of something like 3nm.”
The way lithography tools compensate for these distortions is by correcting at each reticle field to align the backside connection to the TSVs. “In the meantime, you have bonded the wafer to another wafer, you have removed the silicon substrate, you have done a wafer bonding operation — a lot of ‘torture,'” Beyne said. “And if you expect the transistors to be where you think they will be, that may not be the case because all these process steps distort the wafer. So you correct your lithography with the known displacement by measuring, seeing where the contact should be, and if it’s not there, correcting in the right direction. Amazingly, it works.”
Other changes
One of the challenges with having metal layers on the backside of the wafer is that it’s harder to debug the chip, which is typically achieved through the silicon’s backside. “We did lose some capability, like where you could come in and trim things or disconnect a transistor,” Fischer said. “But engineers are clever. And a lot of this is centered around the fact that the backside is highly redundant. So if you need to cut away some stuff, you can still ensure sufficient power delivery while doing the debug. We were able to get the debug process down to a day and a half.”
In addition, the backside integration approach can impact the stress distribution within the active device, potentially modifying the electrical characteristics of the transistors. For instance, the mechanical stress induced by the backside metallization and TSVs can influence the channel strain in gate-all-around transistors, which directly affects carrier mobility and drive current.
Simulating these new stress profiles is important because stress varies in the x, y and z directions of devices. Stress management is a critical aspect of semiconductor device performance, particularly in advanced transistor architectures such as gate-all-around (GAA) transistors,” said Sam Sarkar, senior semiconductor process and integration engineer for Semiverse Solutions at Lam Research. He emphasized the impact of wafer thinning and TSV formation on the stress profile and lithography alignment. “These processes result in new challenges in terms of wafer handling, alignment precision, and thermal budget management.”
Keeping the wafers flat before and after bonding to the carrier wafer is also very difficult. “If you have two flat wafers, they will not be flat after bonding because the process induces distortion,” said imec’s Beyne. “The bonders use tricks like bending a wafer during the bonding, so that you kind of do the opposite, and when the wafers come out of the bonder they’re actually flat. But if you thin the wafer, — and you have to — then the bowing of that wafer is the sum of the bowing of the two initial wafers. So you have to make sure that you start with two rather flat wafers. The flatter the starting point, the better the end result.”
On top of that, with backside power, heat generated by the chip is no longer largely unidirectional. In a traditional chip with all frontside metallization, heat is largely distributed through the silicon to the heat sink and to the outside. “With a backside PDN, you have a back-end-of-line in between the silicon that goes to the heatsink and the devices. So there’s a kind of thermal penalty, because you have these less-conductive layers close to the devices. If you can engineer the backside layers to be better heat spreaders, you can offset that disadvantage,” Beyne said. “It’s more a problem of localized hot spots and wanting to spread the heat over a bigger area so it’s manageable.”
Conclusion
Backside power delivery appears poised for implementation in sub-2nm logic devices, especially high-power, high-performance devices where BPDNs can deliver the most benefits in terms of faster switching speed, lower voltage droop, and greater power efficiency.
Overcoming the process challenges involves extreme wafer thinning, wafer bonding, aligning frontside to backside interconnects, and learning to debug advanced devices. Once the first generation of backside power delivery networks is implemented, chipmakers will take on the formidable task of directly connecting the power to transistor source/drains. And that should add a whole new set of challenges for sub-nanometer processing.
Reference
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