Blog Review: Dec. 4

Cell-aware test; open-source EDA; PIPE 5 PHY; parasitic PLLs.


Arm’s Rupal Gandhi digs into the Cell-Aware Test methodology to deterministically target the growing number of defects that occur within the cells, the process of CAT library generation, and compares the static and transition patterns generated.

Cadence’s Paul McLellan shares highlights from the recent WOSET event with a look at the big drivers for the current interest in open-source EDA tools and why current tools create barriers for academic research.

A Synopsys writer details what’s new in the PCIe PIPE 5.1 specification and how the SerDes architecture makes a PIPE 5 PHY protocol agnostic with all the protocol specific logic shifted to the controller, simplifying PHY design.

In a video, Mentor’s Colin Walls walks through the process of testing software integrity in an embedded system.

Silicon Labs’ Kevin Smith dives into parasitic capacitance and inductance and how an independent oscillator can influence or take over a PLL’s output frequency and phase.

ANSYS’ Robert Harwood considers what needs to happen to make fully-autonomous drones a reality, including better sensors, functionally safe and secure software, and deciding how much autonomy we really want.

Eindhoven University of Technology’s Erwin Kessels traces the history of atomic layer deposition from its invention 45 years ago to the recent advent of area-selective deposition and growth in the number of materials that can be prepared by ALD.

VLSI Research’s John West notes that while it’s been a tough year for critical subsystem suppliers, that hasn’t kept them from investing in R&D.

Nvidia’s Scott Martin checks out a startup that uses AIs to monitor honeybee colonies for signs of varroa mites, which can lead to colony collapse, and remotely treat identified infestations.

For a break from reading, watch some of the latest videos:

Why locating security threats in hardware is so difficult, in Finding Hardware Trojans.

Understanding transient and static effects in multi-chip configurations, in Thermal Challenges In Advanced Packaging.

Runaway complexity is making it more difficult and critical to deal with signal integrity in a system context, in Electromagnetic Challenges In High-Speed Designs.

How die-to-die communication is changing as Moore’s Law slows down with different options for different applications, in Die-To-Die Connectivity.

How to speed up manufacturing with inverse lithography technology with complex curvilinear data, in Using Digital Twins And DL In Lithography.

How end applications determine which compute elements to use, in Making Sense Of Inferencing Options.

A very different approach to adding efficiency into processing, in Reducing Data At The Source.

How GDDR6 compares to other memory types and where it works best, in GDDR6 Drilldown: Applications, Tradeoffs And Specs.

Different ways to use ML in semiconductor manufacturing, in Using Machine Learning To Break Down Silos.

How to ensure millimeter wave technology will be reliable enough, in How 5G Affects Test.

How to track movement of objects and match features, in Simultaneous Localization And Mapping.

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