Thermal Challenges In Advanced Packaging

Understanding transient and static effects in multi-chip configurations.

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CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on.

 

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1 comments

Chris Gintz says:

Are you concerned at all about corrosion caused by fluids used to cool the chips or the wiring harness? Liquids and electrons have a tendency to be a bad solution to the heating/thermal problem.

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