tag: flip-chip package

Thermal Challenges In Advanced Packaging

By Ed Sperling - 02 Dec, 2019 - Comments: 2

CT Kao, product management director at Cadence, talks with Semiconductor Engineering about why packaging is so complicated, why power and heat vary with different use cases and over time, and why a realistic power map is essential particularly for AI chips, where some circuits are always on. Interested in more Semiconductor Engineering videos? Sign-up for our YouTube channel here » read more

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