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Blog Review: May 16

USB Dual Mode; shifting left in automotive; Agile hardware; where are new U.S. fabs?

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Synopsys’ Eric Huang looks back at why the USB On-The-Go specification was revolutionary in getting devices talking to each other and how the shift to USB Type-C and Dual Mode means it isn’t needed anymore.

Mentor’s Andrew Macleod examines four different shift-left methodologies and the benefits of each in the context of automotive and autonomous vehicle design.

Cadence’s Paul McLellan checks out RISC-V, Agile hardware design, and two approaches that attempt lower the design cost of a chip by using generators.

SEMI’s Christian Dieseldorff looks at the state of new volume fabs in the U.S., and finds that while a few are adding capacity, don’t expect any new building on the horizon.

Arm’s Kyrylo Tkachov explains recent improvements to the GNU toolchain on Arm platforms, with a focus on increasing performance of applications built with it through updates to GCC and glibc.

Rambus’ Aharon Etengoff notes that as cryptocurrencies gain value, they become a more enticing target for theft, and points to the array of digital heists that happened just last year.

A National Instruments writer checks out the University of Warwick’s new 5G mmWave test platform, which it will use to expand research on how mmWave communications could work in connected and autonomous vehicles.

ANSYS’ Preeti Gupta, Dave Horn, and Susan Coleman reflect on getting kids interested in technology, science, and seeking opportunities.

Cadence’s Meera Collier looks at the oddness of light’s status as both a particle and wave, its quantum behavior, and a simple experiment that changes its outcome based on being observed.

Mentor’s Cristian Filip continues his series on SerDes design with an explaination of JESD COM (JCOM), a newly developed variant of Channel Operating Margin (COM).

Synopsys’ Taylor Armerding rounds up top stories on (in)security this week, including employees posting passwords online, DVR hacks, and blockchain problems.

And don’t miss the blogs featured in last week’s Low Power-High Performance newsletter:

Editor In Chief Ed Sperling contends that new compute models will require significant improvements in both speed and efficiency.

Fraunhofer’s Christoph Sohrmann observes that demand for analog electronics is growing, making it increasingly important to predict future scaling problems.

Rambus’ Frank Ferro points to bandwidth, not compute power, as the big bottleneck in many AI applications.

ANSYS’ Annapoorna Krishnaswamy explains why it’s so important to model self-heat effects and junction temperature variation.

Mentor’s Srinivas Velivala finds that for effective design rule checking, designers need to optimize set-up and documentation in addition to debugging.

Synopsys’ Gordon Cooper argues that advances in neural networks, coupled with rapidly improving cameras and functional safety requirements, require changing how automotive systems are designed.

Cadence’s Dave Pursley examines the shift from high-power, high-performance to low-power, high-performance.

Arm’s Sriram Ragunathan shows how advances in smartphone SoCs are boosting notebook PC capabilities.

Arteris IP’s Ty Garibay points out must-see technologies in the DAC 2018 IP track, from deep learning processors to eFPGAs.



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