Blog Review: Oct. 31

Formal and memories; making chiplets; PIPE 5.1.1 updates; FPGA in data centers.


Mentor’s Joe Hupcey III digs into handling memories effectively with formal through abstraction and the easiest ways to address memory-related inconclusive results.

Cadence’s Paul McLellan explains DARPA’s CHIPS program that aims to lower semiconductor design costs through chiplet-based designs, the current status of the work, and what the next steps will be.

Synopsys’ Sangeeta Kulkarni checks out the latest features in PIPE 5.1.1 that help it keep up with the latest PCIe specification as well as scale up for future enhancements that allow USB, PCIe and DP to transmit over a common PHY.

Applied Materials’ Michael Stewart takes a look at how a wave of investment and acquisitions kicked off the race to build AI accelerator hardware, key areas new startups are focused on, and what he looks for in new investment opportunities.

Intel’s Ron Wilson warns that while FPGAs could offer substantial benefits to data centers, there is a mismatch between traditional FPGA development techniques and the software-dominated, high-level culture of the data center.

NI’s James Kimery takes a look at how satellites could boost the 5G ecosystem by offering wider geographical coverage to hard-to-connect areas and what’s being done to make it a possibility.

Arm’s Simon Segars points to what’s been learned over the past difficult year in security and tactics the industry can use to combat as-yet unknown threats with the latest version of the company’s Security Manifesto.

UltraSoC’s Rupert Baines recounts his experience at the recent RISC-V Day in Tokyo, which points to increasing performance gains for RISC-V based designs and, perhaps, the beginning of changes in Japan’s business culture.

SEMI’s Nishita Rao chats with Ron Polcawich of DARPA on why a new program for rapid MEMS innovation focuses on creating broader access to mature process flows.

Lam Research’s Shelly Miyasato points to technologies being adopted by libraries from automation to allow staff more time with patrons to coding workshops.

And don’t miss the blogs featured in the latest System-Level Design newsletter:

Editor In Chief Ed Sperling observes that the chip industry is finally getting a chance to prove itself on a much bigger scale.

Technology Editor Brian Bailey examines the balance between containing verification costs and success rates.

Consultant Neil Johnson questions the value of the new Portable Stimulus Standard.

OneSpin’s Tom Anderson looks at what a unified project-level view of verification status brings to the table.

Synopsys’ John Swanson digs into the value of offloading neural network operations from the processor with optimized hardware functions.

Mentor’s Megan Marsh and Wei-Lii Tan find that increasingly specialized process technologies mean it’s time to look at new library characterization flows.

eSilicon’s Mike Gianfagna shows why cables help open a new dimension of backplane design for data center and 5G infrastructure.

Cadence’s Frank Schirrmeister contends that collaboration is the way forward for IoT, as evidenced by major partnership announcements.

Coventor’s Steve Shih-Wei Wang points to both the bottlenecks in stacking memory layers and new opportunities for solutions.

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