Simulating energy-driven computing; UVM transaction classes; ten years of RISC-V.
In a blog for Arm, University of Southampton PhD student Sivert Sliper looks at how energy-driven and intermittent computing could be used to power trillions of IoT devices and introduces a SystemC-based simulator for such systems.
Mentor’s Chris Spear explains why transaction classes should extend from uvm_sequence_item rather than uvm_transaction when designing UVM testbenches.
Cadence’s Paul McLellan takes a look back at ten years of RISC-V, from its start in two Berkeley projects through to its massive expansion as a major ISA today.
A Synopsys writer digs into the details of displays with an explanation of color sub sampling and the different color space conversions, plus why it matters.
Rambus’s Frank Ferro and IDC’s Shane Rau discuss the impact of AI on specific hardware systems, training versus inference, and selecting the most appropriate memory for AI/ML applications.
Ansys’ Robert Harwood argues that simulation is necessary to undertake the billions of miles of testing needed to assess safety in automotive and autonomous vehicle development.
SEMI’s Nishita Rao chats with Jens Fabrowsky of Robert Bosch GmbH about challenges facing the MEMS industry and how sensor companies are evolving to meet market demands.
For a change from reading, watch one of our latest videos:
Find out how to ensure consistent performance in the real world, in 112G SerDes Reliability.
Challenges At 3/2nm present new structures, processes and yield/performance issues.
Explore how memory choices affect power and performance, in Memory Access In AI Systems.
When comparing eFPGAs Vs. FPGA Chiplets, which approach works best where?
Find out some techniques to predict failures and improve reliability, in Ins And Outs Of In-Circuit Monitoring.
All AI chips are not the same, but there are commonalities, in 3 Types Of AI Hardware.
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